TE28F320B3BC90 datasheet(16/58 Pages) INTEL

16 / 58 page

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

3UHOLPLQDU\

When the device is in read array mode, four control signals control data output:

• WE# must be logic high (VIH)

• CE# must be logic low (VIL)

• OE# must be logic low (VIL)

• RP# must be logic high (VIH)

In addition, the address of the desired location must be applied to the address pins. If the device is

not in read array mode, as would be the case after a program or erase operation, the Read Array

command (FFH) must be written to the CUI before array reads can take place.

NOTE: See Appendix A for mode transition information.

Table 4.

Command Codes and Descriptions

Code

Device Mode

Description

00, 01,

60, 2F,

C0, 98

Invalid/

Reserved

Unassigned commands that should not be used. Intel reserves the right to redefine these

codes for future functions.

Read Array

Places the device in read array mode, such that array data will be output on the data pins.

Program Set-Up

This is a two-cycle command. The first cycle prepares the CUI for a program operation. The

second cycle latches addresses and data information and initiates the WSM to execute the

Program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read

Array command is required after programming to read array data. See Section 3.2.4.

Alternate

Program Set-Up

(See 40H/Program Set-Up)

Erase Set-Up

Prepares the CUI for the Erase Confirm command. If the next command is not an Erase

Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a “1,”

(b) place the device into the read status register mode, and (c) wait for another command. See

Section 3.2.5.

Erase Confirm

Program / Erase

Resume

If the previous command was an Erase Set-Up command, then the CUI will close the address

and data latches, and begin erasing the block indicated on the address pins. During erase, the

device will only respond to the Read Status Register and Erase Suspend commands. The

device will output status register data when CE# or OE# is toggled.

If a program or erase operation was previously suspended, this command will resume that

operation

Program / Erase

Suspend

Issuing this command will begin to suspend the currently executing program/erase operation.

The status register will indicate when the operation has been successfully suspended by

setting either the program suspend (SR.2) or erase suspend (SR.6) and the WSM status bit

(SR.7) to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the

state of all input control pins except RP#, which will immediately shut down the WSM and the

remainder of the chip if it is driven to VIL. See Section 3.2.4.1 and Section 3.2.4.1.

Read Status

This command places the device into read status register mode. Reading the device will output

the contents of the status register, regardless of the address presented to the device. The

device automatically enters this mode after a program or erase operation has been initiated.

See Section 3.2.3.

Clear Status

The WSM can set the block lock status (SR.1) , VPP status (SR.3), program status (SR.4), and

erase status (SR.5) bits in the status register to “1,” but it cannot clear them to “0.” Issuing this

command clears those bits to “0.”

Read Identifier

Puts the device into the intelligent identifier read mode, so that reading the device will output

the manufacturer and device codes (A0 = 0 for manufacturer, A0 = 1 for device, all other

address inputs must be 0). See Section Section 3.2.2.

TE28F320B3BC90 Datasheet(PDF) 16 Page - Intel Corporation

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