TE28F320B3BC90 datasheet(22/58 Pages) INTEL

22 / 58 page

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

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3.5.1

Active Power

With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer

to the DC Characteristic tables for ICC current values. Active power is the largest contributor to

overall system power consumption. Minimizing the active current could have a profound effect on

system power consumption, especially for battery-operated devices.

3.5.2

Automatic Power Savings (APS)

Automatic Power Savings provides low-power operation during read mode. After data is read from

the memory array and the address lines are quiescent, APS circuitry places the device in a mode

where typical current is comparable to ICCS. The flash stays in this static state with outputs valid

until a new location is read.

3.5.3

Standby Power

With CE# at a logic-high level (VIH) and device in read mode, the flash memory is in standby

mode, which disables much of the device’s circuitry and substantially reduces power consumption.

Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE#

transitions to a logic-high level during erase or program operations, the device will continue to

perform the operation and consume corresponding active power until the operation is completed.

System engineers should analyze the breakdown of standby time versus active time and quantify

the respective power consumption in each mode for their specific application. This will provide a

more accurate measure of application-specific power and energy requirements.

3.5.4

Deep Power-Down Mode

The deep power-down mode is activated when RP# = VIL (GND ± 0.2 V). During read modes,

RP# going low de-selects the memory and places the outputs in a high impedance state. Recovery

from deep power-down requires a minimum time of tPHQV (see AC Characteristics—Read

Operations, Section 4.5).

During program or erase modes, RP# transitioning low will abort the in-progress operation. The

memory contents of the address being programmed or the block being erased are no longer valid as

the data integrity has been compromised by the abort. During deep power-down, all internal

circuits are switched to a low power savings mode (RP# transitioning to VIL or turning off power to

the device clears the status register).

3.6

Power-Up/Down Operation

The device is protected against accidental block erasure or programming during power transitions.

Power supply sequencing is not required, since the device is indifferent as to which power supply,

VPP or VCC, powers-up first.

TE28F320B3BC90 Datasheet(PDF) 22 Page - Intel Corporation