TE28F320B3BC90 datasheet(14/58 Pages) INTEL

14 / 58 page

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

3UHOLPLQDU\

NOTES:

1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15].

2. X must be VIL, VIH for control pins and addresses.

3. See

DC Characteristics for VPPLK, VPP1, VPP2, VPP3, VPP4 voltages.

4. Manufacturer and device codes may also be accessed in read identifier mode (A1–A21 = 0). See Table 5.

5. Refer to Table 6 for valid DIN during a write operation.

6. To program or erase the lockable blocks, hold WP# at VIH.

7. RP# must be at GND

± 0.2 V to meet the maximum deep power-down current specified.

3.1.1

Read

The flash memory has four read modes available: read array, read identifier, read status and read

query. These modes are accessible independent of the VPP voltage. The appropriate Read Mode

command must be issued to the CUI to enter the corresponding mode. Upon initial device power-

up or after exit from reset, the device automatically defaults to read array mode.

CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection

control; when active it enables the flash memory device. OE# is the data output control and it

drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at

VIH. Figure 7 illustrates a read cycle.

3.1.2

Output Disable

With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins are placed in a

high-impedance state.

3.1.3

Standby

Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby

mode, which substantially reduces device power consumption without any latency for subsequent

read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If

deselected during program or erase operation, the device continues to consume active power until

the program or erase operation is complete.

3.1.4

Deep Power-Down / Reset

From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a high-

impedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required

until the initial read access outputs are valid. A delay (tPHWL or tPHEL) is required after return from

reset before a write can be initiated. After this wake-up interval, normal operation is restored. The

CUI resets to read array mode, and the status register is set to 80H. This case is shown in

Figure 9A.

Table 3.

Bus Operations(1)

Mode

Note

RP#

CE#

OE#

WE#

DQ0–7

DQ8–15

Read (Array, Status, or Identifier)

2–4

VIH

VIL

VIH

DOUT

Output Disable

VIH

VIL

VIH

High Z

Standby

VIH

High Z

Reset

2, 7

VIL

High Z

Write

2, 5–7

VIH

VIL

VIH

VIL

DIN

TE28F320B3BC90 Datasheet(PDF) 14 Page - Intel Corporation

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