IT8712F datasheet(13/189 Pages) ITE

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IT8712F V0.81

vii

Contents

9.8.2

Operation............................................................................................................................ 129

9.8.3

Connection of IFD to ICC Socket ....................................................................................... 129

9.8.4

Baud Rate Relationship Between UART and Smart Card Interface .................................. 130

9.8.5

Waveform Relationship ...................................................................................................... 130

9.8.6

Clock Divider ...................................................................................................................... 130

9.8.7

Waveform Example of Activation/Deactivation Sequence ................................................. 131

9.8.8

ATR and PTS Structure...................................................................................................... 132

9.8.9

Smart Card Operating Sequence Example ........................................................................ 133

9.9

Parallel Port..................................................................................................................................... 134

9.9.1

SPP and EPP Modes ......................................................................................................... 134

9.9.2

EPP Mode Operation.......................................................................................................... 136

9.9.3

ECP Mode Operation ......................................................................................................... 137

9.10 Keyboard Controller (KBC).............................................................................................................. 143

9.10.1 Host Interface ..................................................................................................................... 144

9.10.2 Data Registers and Status Register ................................................................................... 144

9.10.3 Keyboard and Mouse Interface .......................................................................................... 145

9.10.4 KIRQ and MIRQ ................................................................................................................. 145

9.11 Consumer Remote Control (TV Remote) IR (CIR) ......................................................................... 146

9.11.1 Overview............................................................................................................................. 146

9.11.2 Features ............................................................................................................................. 146

9.11.3 Block Diagram .................................................................................................................... 146

9.11.4 Transmit Operation............................................................................................................. 147

9.11.5 Receive Operation.............................................................................................................. 147

9.11.6 Register Descriptions and Address .................................................................................... 147

9.11.6.1 CIR Data Register (DR) ......................................................................................... 148

9.11.6.2 CIR Interrupt Enable Register (IER) ...................................................................... 148

9.11.6.3 CIR Receiver Control Register (RCR) ................................................................... 149

9.11.6.4 CIR Transmitter Control Register 1 (TCR1) .......................................................... 150

9.11.6.5 CIR Transmitter Control Register (TCR2) ............................................................. 151

9.11.6.6 CIR Baud Rate Divisor Low Byte Register (BDLR)................................................ 154

9.11.6.7 CIR Baud Rate Divisor High Byte Register (BDHR) .............................................. 154

9.11.6.8 CIR Transmitter Status Register (TSR) ................................................................. 154

9.11.6.9 CIR Receiver FIFO Status Register (RSR)............................................................ 155

9.11.6.10 CIR Interrupt Identification Register (IIR)............................................................... 155

9.12 Game Port Interface........................................................................................................................ 156

9.12.1 Game Port (Base+0h) ........................................................................................................ 156

9.13 MIDI Interface.................................................................................................................................. 156

9.13.1 MPU-401 Register Interface ............................................................................................... 156

9.13.2 Operation............................................................................................................................ 157

10. DC Electrical Characteristics ..................................................................................................................... 158

11. AC Characteristics (VCC = 5V

± 5%, Ta = 0°C to + 70°C) ........................................................................ 161

11.1 Clock Input Timings ........................................................................................................................ 161

11.2 LCLK (PCICLK) and LRESET Timings ........................................................................................... 161

11.3 LPC and SERIRQ Timings.............................................................................................................. 162

11.4 Serial Port, ASKIR, SIR and Consumer Remote Control Timings .................................................. 163

11.5 Modem Control Timings .................................................................................................................. 163

11.6 Floppy Disk Drive Timings .............................................................................................................. 164

11.7 EPP Address or Data Write Cycle Timings..................................................................................... 165

11.8 EPP Address or Data Read Cycle Timings..................................................................................... 166

11.9 ECP Parallel Port Forward Timings ................................................................................................ 166

11.10 ECP Parallel Port Backward Timings............................................................................................. 167

11.11 RSMRST#, PWROK1/2, and ACPI Power Control Signals Timings.............................................. 167

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