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AT2004
4 Channels ADPCM Processor with Echo Cancellation and Conferencing
Page 22 of 25
©2001 Atelic System, Inc
Master Clock/Reset
(0
°C to 70°C)
AC Electrical Characteristics
(VDD=3.3V+20%-10%)
Parameter
Symbol
Minimum
Typical
Maximum
Units
Notes
MCLK
Period
tPM
69.84
100
125
ns
1
MCLK
Rise/Fall
Times
tRM, tFM
10
ns
RSTZ
Pulse
Width
tRST
1
ms
Note:
1. MCLK = 14MHz or 10MHz.
Serial Port
(0
°C to 70°C)
AC Electrical Characteristics
(VDD=3.3V+20%-10%)
Parameter
Symbol
Minimum
Typical
Maximum Units
Notes
SDI to SCLK Set Up
tDC
55
ns
1
SCLK Period
tP
1
µs
1
SCLK to SDI Hold
tCDH
55
ns
1
SCLK Low Time
tCL
250
500
ns
1
SCLK High Time
tCH
250
500
ns
1
SCLK Rise and Fall Time
tR, tF
100
ns
1
SCSZ to SCLK Setup
tCC
50
ns
1
SCLK to SCSZ Hold
tCCH
250
ns
1
SCSZ Inactive Time
tCWH
250
ns
1
SCLK Setup to SCSZ
Falling
tSCC
50
ns
1
Note:
1. Measured at VIH = 2.0V, VIL = 0.8V, and 10ns maximum rise and fall time.
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