FS98O24 datasheet(48/77 Pages) FORTUNE

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ADC Application Guide

The ADC used in FS98O24 is a - ADC with fully differential inputs and fully differential reference voltage

inputs. Its maximum output is 15625. The conversion equation is as follows:

Vro

VRL

VRH

Vio

VIL

VIH

15625

Dout







G is ADC input gain. (refer to Section 10.1 ADC operation step 6)



VIH is ADC’s positive input voltage



VIL is ADC’s negative input voltage



Vio is ADC’s offset on the input terminals (Vio could be measured by using AZ register flag. See Section

11.4)



VRH is the voltage at the positive input of Reference Voltage



VRL is the voltage at the negative input of Reference Voltage



Vro is the offset on the input terminals of Reference Voltage (Generally speaking, Vro could be ignored)



The value (VRH-VRL+Vro) should be positive.



When G * (VIH-VIL+Vio) / (VRH-VRL+Vro)

 1, Dout=15625



When G * (VIH-VIL+Vio) / (VRH-VRL+Vro)

 -1, Dout=-15625

9.1. ADC Output Format

CPU can read ADO[14:0] as ADC’s 15

-bit output. Note that the output is in 2’s complement format. The 14th bit

of ADO[14:0] is sign bit. When the sign bit is cleared, the ADC output denotes a positive number, When the sign

bit is set, the ADC output denotes a negative number.

Example:

ADO[15:0] = 0X257FH, then Dout = 9599.

ADO[15:0] = 0XE2F7H, then Dout = - (not (E2F7H) +1) = -7433.

9.2. ADC Linear Range

ADC is close to saturation when G * (VIH-VIL+Vio) / (VRH-VRL+Vro) is close to 1, and has good linearity in

the range of 0.95.

9.3. ADC Output Rate and Settling Time

ADC output is the results of sigma delta modulator and the comb filter. The analog input signal needs to be

sampled N6 times and processed by the ADC and then the user could get one digital output. Generally

speaking, the more times ADC samples the analog input signal, the more precise the digital output is.

When the user decides the sampling frequency and sampling counts, and then enables the ADC module, ADC

module will send out a 15-bit signed digital output data every sampling N times and trigger the ADC interrupt.

In fact, every ADC output includes previous 2*N times sampling results. Generally speaking, if ADC inputs,

reference voltage, ADG, AZ are switched, the previous two ADC digital outputs are normally unstable ones, the

third output and beyond are stable.

9.4. ADC Input Offset

ADC Input Offset Vio is NOT a constant. It drifts with temperature and common mode voltage at the inputs.

To get a correct ADC result, Doff(ADC input offset digital output) should be deducted from the Dout. The

instruction is as follows:

6 ‘N times’ could be decided by setting ADM register flag (Please refer to Section 10.1).

FS98O22 ADC sampling frequency is decided by M1_CK( Please refer to Section 5.3).

FS98O24 Datasheet(PDF) 48 Page - Fortune Semiconductor Corp.

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