IRU3038CS datasheet(10/18 Pages) IRF

10 / 18 page

Rev. 2.0

09/12/02

IRU3038

www.irf.com

Place second pole at the ESR zero.

Check if R8 >

If R8 is too small, increase R7 and start from step 2.

Place second zero around the resonant frequency.

Use equation (1) to calculate R5:

These design rules will give a crossover frequency ap-

proximately one-tenth of the switching frequency. The

higher the band width, the potentially faster the load tran-

sient speed. The gain margin will be large enough to

provide high DC-regulation accuracy (typically -5dB to -

12dB). The phase margin should be greater than 45

8 for

overall stability.

IC Quiescent Power Dissipation

Power dissipation for IC controller is a function of ap-

plied voltage, gate driver loads and switching frequency.

The IC's maximum power dissipation occurs when the

IC operating with single 12V supply voltage (Vcc=12V

and Vc

≅24V) at 400KHz switching frequency and maxi-

mum gate loads.

This IC's power dissipation results to an excessive tem-

perature rise and should be considered when using

IRU3038 for such an application.

Layout Consideration

The layout is very important when designing high fre-

quency switching converters. Layout will affect noise

pickup and can cause a good design to perform with

less than expected results.

Start to place the power components. Make all the con-

nections in the top layer with wide, copper filled areas.

The inductor, output capacitor and the MOSFET should

be close to each other as possible. This helps to reduce

the EMI radiated by the power traces due to the high

switching currents through them. Place input capacitor

directly to the drain of the high-side MOSFET. To reduce

the ESR, replace the single input capacitor with two par-

allel units. The feedback part of the system should be

kept away from the inductor and other noise sources

and be placed close to the IC. In multilayer PCB, use

one layer as power ground plane and have a separate

control circuit ground (analog ground), to which all sig-

nals are referenced. The goal is to localize the high cur-

rent path to a separate loop that does not interfere with

the more sensitive analog control function. These two

grounds must be connected together on the PC board

layout at a single point.

R5 =

3 R6

VREF

VOUT - VREF

R6 =

- R8

p 3 C10 3 FZ2

FZ2 = FLC

R8 =

p 3 C10 3 FP2

FP2 = FESR

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