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PCM1780 Datasheet(PDF) 17 Page - Texas Instruments

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Part # PCM1780
Description  24-Bit, 192-kHz Sampling, Enhanced Multilevel, Delta-Sigma, Audio Digital-to-Analog Converter
PDF  31 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCM1780 Datasheet(HTML) 17 Page - Texas Instruments

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SOFTWARE CONTROL (PCM1780/82)
Register Write Operation
MSB
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
LSB
Register Index (or Address)
Register Data
R0001-01
IDX0
D7
D6
D4
D5
D3
D2
D1
D0
0
MS
MC
MD
X
0
IDX6
X
IDX1
IDX2
IDX3
IDX4
IDX5
IDX6
X
T0048-01
Control Interface Timing Requirements
PCM1780, PCM1781, PCM1782
SLES132A – MARCH 2005 – REVISED APRIL 2005
The PCM1780/82 has many programmable functions that can be controlled in the software control mode; the
functions are controlled by programming the internal registers using MS, MC, and MD.
The serial control interface is a 3-wire serial port which operates asynchronously to the audio serial interface.
The serial control interface is used to program the on-chip mode registers. The control interface includes MD
(pin 4), MC (pin 3), and MS (pin 2). MD is the serial data input, used to program the mode registers. MC is the
serial bit clock, used to shift data into the control port. MS is the select input, used to enable the mode control
port.
All write operations for the serial control port use 16-bit data words. Figure 24 shows the control data word
format. The most significant bit must be a 0. Seven bits, labeled IDX[6:0], set the register index (or address) for
the write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specified
by IDX[6:0].
Figure 25 shows the functional timing diagram for writing to the serial control port. MS is held at a logic-1 state
until a register needs to be written. To start the register write cycle, MS is set to logic 0. Sixteen clocks are then
provided on MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle has
completed, MS is set to logic 1 to latch the data into the indexed mode control register.
Figure 24. Control Data Word Format for MD
Figure 25. Register Write Operation
Figure 26 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for
proper control port operation.
17



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