SH7268/SH7269 Group

Transmission/Reception of Renesas SPDIF Interface

R01AN1188EJ0100 Rev.1.00

Page 4 of 23

Jul. 27, 2012

2.

Operation Confirmation Conditions

The sample code accompanying this application note has been run and confirmed under the conditions below.

Table 2.1 Operation Confirmation Conditions

Item

Contents

MCU used

SH7269

Operating frequency

CPU internal clock (I

φ): 266.67MHz

Internal clock (B

φ): 133.33MHz

Peripheral clock 1 (P1

φ): 66.67MHz

Peripheral clock 0 (P0

φ): 33.33MHz

Operating voltage

Source Power (I/O): 3.3V

Source Power (internal): 1.25V

Integrated development

environment

Renesas Electronics Corporation

High-performance Embedded Workshop Ver. 4.07.00

Renesas Electronics Corporation

SuperH RISC engine Family C/C++ compiler package

Ver.9.03 Release 02

C compiler

Compile option

-cpu=sh2afpu -fpu=single. -include="$(WORKSPDIR)\inc"

-object="$(CONFIGDIR)\$(FILELEAF).obj" -debug -gbr=auto

-chgincpath -errorpath -global_volatile=0 -opt_range=all -infinite_loop=0

-del_vacant_loop=0 -struct_alloc=1 -nologo

Board used

R0K572690C000BR

3.

Reference Application Note

For additional information associated with this document, refer to the following application note.

• SH7262/SH7264 Group Example of Initialization (RJ06B0998)