SH7268/SH7269 Group

Transmission/Reception of Renesas SPDIF Interface

4.

Peripheral Functions

This chapter provides supplementary information on RSPDIF, which basic information is described in the hardware

manual.

4.1

Channel Configuration

The RSPDIF consists of two channels. The directions of transmission/reception for each channel are fixed. The channel

0 is used for transmission, and the channel 1 is used for reception.

4.2

Transfer Data

In addition to the audio data which includes sound data, user information and channel status information will also be

transmitted and received in the SPDIF. Therefore, it is necessary to write/read these data to/from the RSPDIF register.

Figure 4.1 shows the Register Group for Reading/Writing Transfer Data. The length of 32-bit is required.

Renesas SPDIF interface

Tranfer rate:

384 words/block

Channel 1 (L)

Channel 2 (R)

Audio data

Transmitter DMA audio data register (TDAD)

Receiver DMA audio data register (RDAD)

DMAC

Channel 1 (L)

Channel 2 (R)

Channel 1 (L)

Channel 2 (R)

Channel 1 (L)

Channel 2 (R)

Channel 1 (L)

Channel 2 (R)

Channel 1 (L)

Channel 2 (R)

Transmitter channel 1 audio data register (TLCA)

Receiver channel 1 audio data register (LCA)

(Unused during DMA transfer)

Transmitter channel 2 audio data register (TRCA)

Receiver channel 2 audio data register (RRCA)

(Unused during DMA transfer)

Channel 1 (L)

Channel 2 (R)

Channel 1 (L)

Channel 2 (R)

User information

Transmitter user data register (TUI)

Receiver user data register (RUI)

Transfer rate:

12 words/block

Channel 1 (L)

Channel 2 (R)

Channel status

information

Transmitter channel 1 status register (TLCS)*

Receiver channel 1 status register (RLCS)

Transmitter channel 2 status register (TRCS)*

Receiver channel 2 status register (RRCS)

Transfer rate:

1 word/block

[Note] The transmitter module transmits the values of TLCS register and TRCS register for the point at which

transmission of each block starts as channel status values. Therefore, if the same value as used last

time will be transmitted, rewriting for the register is not required. When rewriting, it should be done

during the period that the transfer is not executed (between frame 31 and the beginning of the next

block).

Figure 4.1 Register Group for Reading/Writing Transfer Data

R01AN1188EJ0100 Rev.1.00

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Jul. 27, 2012