SH7269 datasheet(20/26 Pages) RENESAS

20 / 26 page

SH7268/SH7269 Group

Transmission/Reception of Renesas SPDIF Interface

6.8.7

Initialization of DMAC Channel 5

Figure 6.9 shows the Initialization of DMAC Channel 5.

STBCR2 register

MSTP8 bit ← 0

: Allow clock supply

io_init_dmac5

Allow DMAC clock supply

Prohibit operation of

DMAC channel 5

Set transfer method

Set transfer request source

return

CHCR5 register

DE bit ← 0

: Prohibit operation of DMAC channel 5

CHCR5 register ← H'3010 4814

TC bit = 0

: Provide one transfer per request

RLDSAR bit = 1

: SAR reload ON

RLDDAR bit = 1

: DAR reload ON

TEMASK bit = 1

: Continue DMA transfer even if TE bit is set

HIE bit = 0

: Prohibit interrupt when half number of transfers have been completed

DM bit = B'01

: Increase destination address

SM bit = B'00

: Fix source address

RS bit = B'1000

: Select transfer request source by extension resource selector (DMARS)

TB bit = 0

: Cycle steal mode

TS bit = B'10

: Transfer by the longword (4-byte)

IE bit = B'1

: Allow transfer completion interrupt

Set transfer source address

SAR5 register ← &(SPDIF.RDAD)

Specify RSPDIF receiver DMA audio data register as a transfer source address

Set transfer destination address

DAR5 register ← g_spdin.a_buf

Specify start address of audio receiver buffer as a transfer destination address

Set the number of transfers

DMATCR5 register ← (192 * 2)

Set the number of transfers to 384 times (audio data for one block)

DMARS2 register

CH5 bit ← H'0A

: Specify RSPDIF receiver module as a transfer request source

Provide common setting for

all channels

DMAOR register ← H'0007

CMS bit = B'00

: Select normal for cycle steal mode

DME bit = 1

: Allow operation of all channels

Set interrupt priority level

IPR07 register

_DMAC5 bit ← 3

: Set priority level 3 for DMAC channel 5

transfer completion interrupt (interrupt allowed)

Allow operation of DMAC channel 5

CHCR5 register

DE bit ← 1

: Allow operation of DMAC channel 5

Figure 6.9 Initialization of DMAC Channel 5

R01AN1188EJ0100 Rev.1.00

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Jul. 27, 2012

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