LAN9117 datasheet(71/131 Pages) SMSC

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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

Datasheet

SMSC LAN9117

Revision 1.1 (05-17-05)

DATASHEET

5.1

5.2

RX and TX FIFO Ports

The LAN9117 contains four host-accessible FIFOs: the RX Status, RX data, TX Status, and TX data

FIFOs. The sizes of the RX and TX data FIFOs, as well as the RX Status FIFO are configurable

through the CSRs.

5.2.1

RX FIFO Ports

The RX data Path consists of two Read-Only FIFOs; the RX Status and data. The RX Status FIFO can

be read from two locations. The RX Status FIFO Port will perform a destructive read, thus “Popping”

the data from the RX Status FIFO. There is also the RX Status FIFO PEEK location. This location

allows a non-destructive read of the top (oldest) location of the FIFO.

The RX data FIFO only allows destructive reads. It is aliased in 8 DWORD locations (accessed from

the bus interface as 8 pairs of atomic 16-bit accesses). The host may access any of the locations since

they all contain the same data and perform the same function.

5.2.2

TX FIFO Ports

The TX data Path consists of two FIFOs, the TX status and data. The TX Status FIFO can be read

from two locations. The TX Status FIFO Port will perform a destructive read, thus “Popping” the data

from the TX Status FIFO. There is also the TX Status FIFO PEEK location. This location allows a non-

destructive read of the top (oldest) location of the FIFO.

SYMBOL

DESCRIPTION

Read Only: If a register is read only, writes to this register have no effect.

Write Only: If a register is write only, reads always return 0.

R/W

Read/Write: A register with this attribute can be read and written

R/WC

Read/Write Clear: A register bit with this attribute can be read and written. However, a write

of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.

Read to Clear: A register bit with this attribute is cleared when read.

Latch Low: Clear on read of register

Latch High: Clear on read of register

Self-Clearing

NASR

Not Affected by Software Reset

Reserved

Bits

Unless otherwise stated, reserved fields must be written with zeros to ensure future

compatibility. The value of reserved bits is not guaranteed on a read.

Reserved

Registers

In addition to reserved bits within a register, the LAN9117 contains address locations in the

configuration space that are marked “Reserved. When a “Reserved” register location is read,

a random value can be returned. Registers that are marked as “Reserved” must not be

modified by system software. Writes to “Reserved” registers may cause system failure.

Default

Value Upon

Reset

Upon a Reset (System reset, Software Reset, or POR), the LAN9117 sets its internal

configuration registers to predetermined default states. The default state represents the

minimum functionality feature set required to successfully bring up the system. Hence, it does

not represent the optimal system configuration. It is the responsibility of the system

initialization software to properly determine the operating parameters and optional system

features that are applicable, and to program the LAN9117 registers accordingly.

LAN9117 Datasheet(PDF) 71 Page - SMSC Corporation

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