LAN9117 datasheet(89/131 Pages) SMSC

89 / 131 page

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

Datasheet

SMSC LAN9117

Revision 1.1 (05-17-05)

DATASHEET

5.3.16

GPT_CNT-General Purpose Timer Current Count Register

This register reflects the current value of the GP Timer.

5.3.17

ENDIAN—Endian Control

This register controls the Endianess of the LAN9117.

Offset:

90h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31-16

Reserved

15-0

General Purpose Timer Current Count (GPT_CNT). This 16-bit field

reflects the current value of the GP Timer.

FFFFh

Offset:

98h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Endian. If this field is set to 0xFFFFFFFFh, the LAN9117 is configured to

operate with most host big-endian processors using a 16-bit interface. If this

field is set to anything else, the LAN9117 is configured to operate with native

16-bit Little-Endian processors.

Notes:

■ Please refer to Section 3.6.1, "Bus Writes" for additional information.

■ The value of this field is only significant when configured for 16-bit

operation.

R/W

NASR

00000000h

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