TFP513

TI PanelBus DIGITAL TRANSMITTER

SLLS611 − AUGUST 2004

5

POST OFFICE BOX 655303

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NUMBER

I/O

DESCRIPTION

Configuration/Programming Pins (Continued)

PD

10

I

Power down (active low). In the power-down state only the digital I/O buffers and I2C interface remain

active.

When I2C is disabled (ISEL = low), a high level selects the normal operating mode. A low level selects

the power-down mode.

When I2C is enabled (ISEL = high), the power-down state is selected through I2C. In this configuration,

the PD pin must be tied to GND.

Note: The default register value for PD is low, so the device is in power-down mode when I2C is first

enabled or after an I2C RESET.

RDA

RCL

7

8

I/O

These terminals are the I2C interface to the internal HDCP key EEPROM. Each terminal requires a

pullup resistor in the range of 900

Ω to 5 kΩ connected to VDD.

VREF

3

I

Input reference voltage. Selects the swing range of the digital data inputs (DATA[23:0], DE, HSYNC,

VSYNC, and IDCK

±).

For high-swing 3.3-V input signal levels, VREF must be tied to VDD.

For low-swing input signal levels, VREF must be set to half of the maximum input voltage level. See the

recommended operating conditions section for the allowable range for VREF.

The desired VREF voltage level is typically derived using a simple voltage divider circuit.

Reserved

NC

49

I

No connection required. If this terminal is connected, tie it to VDD.

RESERVED

34, 35

I

These pins are reserved and must be tied to GND for normal operation.

DVI Differential Signal Output Pins

TFADJ

19

I

Full-scale adjust. This pin controls the amplitude of the DVI output voltage swing, determined by the

value of the pullup resistor R(TFADJ) connected to TVDD.

TX0+

TX0−

25

24

O

Channel-0 DVI differential output pair. TX0

± transmits the 8-bit blue pixel data during active video and

HSYNC and VSYNC during the blanking interval.

TX1+

TX1−

28

27

O

Channel-1 DVI differential output pair. TX1

± transmits the 8-bit green pixel data during active video and

CTL[1] during the blanking interval.

TX2+

TX2−

31

30

O

Channel-2 DVI differential output pair. TX2

± transmits the 8-bit red pixel data during active video and

CTL[3:2] during the blanking interval.

TXC+

TXC−

22

21

O

DVI differential output clock.

Power and Ground Pins

DGND

16, 48, 64

Digital ground

DVDD

1, 12, 33

Digital power supply. Must be set to 3.3 V nominal

PGND

17

PLL ground

PVDD

18

PLL power supply. Must be set to 3.3 V nominal

TGND

20, 26, 32

Transmitter differential output driver ground

TVDD

23, 29

Transmitter differential output driver power supply. Must be set to 3.3 V nominal