TFP513

TI PanelBus DIGITAL TRANSMITTER

SLLS611 − AUGUST 2004

11

POST OFFICE BOX 655303

T.M.D.S. pixel data and control signal encoding

For T.M.D.S., only one of two possible T.M.D.S. characters for a given pixel is transmitted at a given time. The

transmitter keeps a running count of the number of 1s and 0s previously sent and transmits the character that

minimizes the number of transitions and approximate a dc balance of the transmission line. Three T.M.D.S.

channels transmit RGB pixel data during the active video interval (DE = high). These same three channels also

transmit HSYNC, VSYNC, and three control signals, CTL[3:1], during the inactive display or blanking interval

(DE = low). The following table maps the transmitted output data to the appropriate T.M.D.S. output channel

in a DVI-compliant system.

INPUT PINS

(VALID FOR DE = high)

T.M.D.S. OUTPUT CHANNEL

TRANSMITTED PIXEL DATA

ACTIVE DISPLAY (DE = high)

DATA[23:16]

Channel 2 (TX2

±)

Red[7:0]

DATA[15:8]

Channel 1 (TX1

±)

Green[7:0]

DATA[7:0]

Channel 0 (TX0

±)

Blue[7:0]

INPUT PINS

(VALID FOR DE = low)

T.M.D.S. OUTPUT CHANNEL

TRANSMITTED CONTROL DATA

BLANKING INTERVAL (DE = low)

CTL3, CTL2 (see Note 8)

Channel 2 (TX2

±)

CTL[3:2]

CTL1 (see Note 8)

Channel 1 (TX1

±)

CTL[1]

HSYNC, VSYNC

Channel 0 (TX0

±)

HSYNC, VSYNC

NOTE 8: The TFP513 encodes and transfers the CTL[3:1] inputs during the vertical blanking interval. The

TFP513 internally generates CTL3 for HDCP operation and the CTL[2:1] inputs are reserved for

future use. When DE = high, the CTL and SYNC pins must be held constant.

universal graphics controller interface voltage signal levels

The universal graphics controller interface can operate in the following two distinct voltage modes:

universal graphics controller interface clock inputs

The universal graphics controller interface supports both single-ended and fully differential clock input modes.

In the differential clock input mode, the universal graphics controller interface uses the crossover point between

the IDCK+ and IDCK− signals as the timing reference for latching incoming data (DATA[23:0], DE, HSYNC, and

VSYNC). Differential clock inputs provide greater common-mode noise rejection. The differential clock input

mode is only available in the low-swing mode. In the single-ended clock input mode, the IDCK+ input (pin 57)

must be connected to the single-ended clock source and the IDCK− input (pin 56) must be tied to GND.

The universal graphics controller interface provides selectable 12-bit, dual-edge and 24-bit, single-edge input

clocking modes. In the 12-bit, dual-edge mode, the 12-bit data is latched on each edge of the input clock. In the

24-bit, single-edge mode, the 24-bit data is latched on the rising edge of the input clock when EDGE = 1 and

the falling edge of the input clock when EDGE = 0.

DKEN and DK[3:1] allow the user to compensate the skew between IDCK

± and the pixel data and control

signals. See the description of the CTL_3_MODE register for details.