TFP513

TI PanelBus DIGITAL TRANSMITTER

SLLS611 − AUGUST 2004

24

POST OFFICE BOX 655303

acknowledge by pulling the SDA line low during the ninth clock cycle if it decodes the address as its address.

During subsequent subaddress and data cycles, the TFP513 responds with acknowledge as shown in

Figure 12. The subaddress is auto-incremented after each data cycle.

The transmitting device must not drive the SDA signal during the acknowledge cycle so that the receiving device

may drive the SDA signal low. The master indicates a not acknowledge condition (/A) by keeping the SDA signal

high just before it asserts the stop condition (P). This sequence terminates a read cycle as shown in Figure 13.

In order to minimize the number of bits that must be transferred for the HDCP link integrity check, a second read

format is supported. This access, shown in Figure 14, has an implicit subaddress equal to the starting location

The slave address consists of 7 bits of address along with 1 bit of read/write information (that is, read = 1 and

write = 0) as shown in Figure 12 through Figure 14. For the TFP513 the slave addresses are 0x70 for write

cycles and 0x71 for read cycles.

S

Slave Address

W

A

Subaddress

A

Data

A

Data

A

P

From Master

A Acknowledge

From Slave

S Start condition

P Stop Condition

R Read Condition = 1

W Write Condition = 0

S

Slave Address

W

A

Subaddress

A

Sr

Slave Address

R

A

Data

A

Data

/A

P

From Master

A Acknowledge

From Slave

S Start condition

/A Not acknowledge (SDA high)

P Stop Condition

R Read Condition = 1

Sr Restart Condition

W Write Condition = 0

S

Slave Address

R

A

Data

A

Data

/A

P

From Master

A Acknowledge

From Slave

S Start condition

/A Not acknowledge (SDA high)

P Stop Condition

R Read Condition = 1

Figure 14. HDCP Port Link Integrity Message Read