TFP513

TI PanelBus DIGITAL TRANSMITTER

SLLS611 − AUGUST 2004

12

POST OFFICE BOX 655303

universal graphics controller interface modes

Table 1 is a tabular representation of the different modes for the universal graphics controller interface. The

12-bit mode is selected when BSEL = 0 and the 24-bit mode when BSEL = 1. The 12-bit mode uses dual-edge

clocking and the 24-bit mode uses single-edge clocking. The EDGE input controls the latching edge in 24-bit

mode or the primary latching edge in 12-bit mode. When EDGE = 1, the data input is latched on the rising edge

of the input clock; and when EDGE = 0, the data input is latched on the falling edge of the input clock. A fully

differential input clock is available only in the low-swing mode. Single-ended clocking is not recommended in

the low-swing mode as this decreases common-mode noise rejection.

Table 1. Universal Graphics Controller Interface Options

VREF

BSEL

EDGE

DSEL

BUS WIDTH

LATCH MODE

CLOCK EDGE

CLOCK MODE

0.55 V − 0.9 V

0

0

0

12-bit

Dual-edge

Falling

Differential (see Notes 9 and 10)

0.55 V − 0.9 V

0

0

1

12-bit

Dual-edge

Falling

Single-ended

0.55 V – 0.9 V

0

1

0

12-bit

Dual-edge

Rising

Differential (see Notes 9 and 10)

0.55 V − 0.9 V

0

1

1

12-bit

Dual-edge

Rising

Single-ended

0.55 V – 0.9 V

1

0

0

24-bit

Single-edge

Falling

Single-ended

0.55 V – 0.9 V

1

0

1

24-bit

Single-edge

Falling

Differential (see Notes 9 and 11)

0.55 V – 0.9 V

1

1

0

24-bit

Single-edge

Rising

Single-ended

0.55 V – 0.9 V

1

1

1

24-bit

Single-edge

Rising

Differential (see Notes 9 and 11)

DVDD

0

0

X

12-bit

Dual-edge

Falling

Single-ended (see Note 12)

DVDD

0

1

X

12-bit

Dual-edge

Rising

Single-ended (see Note 12)

DVDD

1

0

X

24-bit

Single-edge

Falling

Single-ended (see Note 12)

DVDD

1

1

X

24-bit

Single-edge

Rising

Single-ended (see Note 12)

NOTES:

9. The differential clock input mode is only available in the low signal swing mode (that is, VREF ≤ 0.9 V).

10. The TFP513 does not support a 12-bit, dual-clock, single-edge input clocking mode.

11. The TFP513 does not support a 24-bit, single-clock, dual-edge input clocking mode.

12. In the high-swing mode (VREF = DVDD), DSEL is a don’t care; therefore, the device is always in the single-ended latch mode.