HD64F2145 datasheet(462/829 Pages) RENESAS

462 / 829 page

Rev. 2.0, 08/02, page 422 of 788

Bit

Bit Name

Initial Value R/W

Description

ICDRE

Transmit Data Write Request Flag

Indicates the ICDR (ICDRT) status in transmit mode.

0: Indicates that the data has been already written to ICDR

(ICDRT) or ICDR is initialized.

1: Indicates that data has been transferred from ICDRT to

ICDRS and is being transmitted, or the start condition has

been detected or transmission has been complete, thus

allowing the next data to be written to.

[Setting conditions]

• When the start condition is detected from the bus line

state with I

2C bus format or serial format.

• When I2C bus mode is switched to formatless (when the

SW bit in DDCSWR is set to 1).

• When data is transferred from ICDRT to ICDRS.

1. When data transmission completed while ICDRE =

0 (at the rise of the 9th clock pulse).

2. When data is written to ICDR in transmit mode after

data transmission was completed while ICDRE = 1.

[Clearing conditions]

• When data is written to ICDR (ICDRT).

• When the stop condition is detected with I2C bus format

or serial format.

• When 0 is written to the ICE bit.

• When the IIC is internally initialized using the CLR3 to

CLR0 bits in DDCSWR.

Note that if the ACKE bit is set to 1 with I

2C bus format thus

enabling acknowledge bit decision, ICDRE is not set when

data transmission is completed while the acknowledge bit

is 1.

When ICDRE is set due to the condition (2) above, ICDRE

is temporarily cleared to 0 when data is written to ICDR

(ICDRT); however, since data is transferred from ICDRT to

ICDRS immediately, ICDRE is set to 1 again. Do not write

data to ICDR when TRS = 0 because the ICDRE flag value

is invalid during the time.

HD64F2145 Datasheet(PDF) 462 Page - Renesas Technology Corp

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