DLPC4422 datasheet(2/49 Pages) TI1

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DLPC4422

DLPS074 – FEBRUARY 2017

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Table of Contents

Features .................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions ......................... 3

Specifications....................................................... 14

6.1

Absolute Maximum Ratings .................................... 14

6.2

ESD Ratings............................................................ 14

6.3

Recommended Operating Conditions ..................... 15

6.4

Thermal Information ................................................ 15

6.5

Electrical Characteristics......................................... 16

6.6

System Oscillators Timing Requirements ............... 18

6.7

Test and Reset Timing Requirements .................... 18

6.8

JTAG Interface: I/O Boundary Scan Application

Timing Requirements ............................................... 19

6.9

Port 1 Input Pixel Timing Requirements ................. 19

6.10

Port 3 Input Pixel Interface (via GPIO) Timing

Requirements........................................................... 20

6.11

DMD LVDS Interface Timing Requirements ......... 21

6.12

Synchronous Serial Port (SSP) Interface Timing

Requirements........................................................... 21

6.13

Programmable Output Clocks Switching

Characteristics ......................................................... 22

6.14

Synchronous Serial Port Interface (SSP) Switching

Characteristics ......................................................... 22

6.15

JTAG Interface: I/O Boundary Scan Application

Switching Characteristics ......................................... 23

Detailed Description ............................................ 27

7.1

Overview ................................................................. 27

7.2

Functional Block Diagram ....................................... 27

7.3

Feature Description................................................. 27

Application and Implementation ........................ 32

8.1

Application Information............................................ 32

8.2

Typical Application .................................................. 32

Power Supply Recommendations ...................... 35

9.1

System Power Regulations ..................................... 35

9.2

System Power-Up Sequence .................................. 35

9.3

Power-On Sense (POSENSE) Support .................. 36

9.4

System Environment and Defaults.......................... 36

Layout................................................................... 37

10.1

Layout Guidelines ................................................. 37

Device and Documentation Support ................. 44

11.1

Device Support...................................................... 44

11.2

Documentation Support ........................................ 45

11.3

Community Resources.......................................... 46

11.4

Trademarks ........................................................... 46

11.5

Electrostatic Discharge Caution ............................ 46

11.6

Glossary ................................................................ 46

Mechanical, Packaging, and Orderable

Information ........................................................... 46

12.1

Package Option Addendum .................................. 47

4 Revision History

DATE

REVISION

NOTES

Initial release.

DLPC4422 Datasheet(PDF) 2 Page - Texas Instruments

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