DLPC4422 datasheet(9/49 Pages) TI1

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DLPC4422

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DLPS074 – FEBRUARY 2017

Product Folder Links: DLPC4422

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Pin Configurations and Functions (continued)

(1)

I/O

(2)

DESCRIPTION

NAME

NO.

PM_ADDR_9

Output Bus A Data bit 0 to DMD.

PM_ADDR_8

PM_ADDR_7

Output Bus A Data bit 1 to DMD.

PM_ADDR_6

PM_ADDR_5

Output Bus A Data bit 2 to DMD.

PM_ADDR_4

PM_ADDR_3

Output Bus A Data bit 3 to DMD.

PM_ADDR_2

PM_ADDR_1

Output Bus A Data bit 4 to DMD.

PM_ADDR_0

PM_WEZ

B12

Output Bus A Data bit 5 to DMD.

PM_OEZ

C13

PM_BLSZ_1

Output Bus A Data bit 6 to DMD.

PM_BLSZ_0

PM_DATA_15

C17

Output Bus A Data bit 7 to DMD.

PM_DATA_14

B16

PM_DATA_13

A16

Output Bus A Data bit 8 to DMD.

PM_DATA_12

A15

PM_DATA_11

B15

Output Bus A Data bit 9 to DMD.

PM_DATA_10

D16

PM_DATA_9

C16

Output Bus A Data bit 10 to DMD.

PM_DATA_8

E14

PM_DATA_7

D15

Output Bus A Data bit 11 to DMD.

PM_DATA_6

C15

PM_DATA_5

B14

Output Bus A Data bit 12 to DMD.

PM_DATA_4

A14

PM_DATA_3

E13

Output Bus A Data bit 13 to DMD.

PM_DATA_2

D14

PM_DATA_1

C14

Output Bus A Data bit 14 to DMD.

PM_DATA_0

B13

PERIPHERAL INTERFACE

IIC0_SCL

A10

I2C Bus 0, Clock. This bus support 400 kHz, fast mode operation. This signal

requires an external pull-up to 3.3-V. The minimum acceptable pull-up value is 1 kΩ.

This input is not 5 V tolerant.

IIC0_SDA

B10

2C Bus 0, Data. This bus support 400 kHz, fast mode operation. This signal requires

an external pull-up to 3.3-V. The minimum acceptable pull-up value is 1 kΩ. This

input is not 5 V tolerant.

SSP0_CLK

AD4

Synchronous Serial Port 0, clock

SSP0_RXD

AD5

Synchronous Serial Port 0, receive data in

SSP0_TXD

AB7

Synchronous Serial Port 0, transmit data out

SSP0_CSZ_0

AC5

Synchronous Serial Port 0, chip select 0 (active low)

SSP0_CSZ_1

AB6

Synchronous Serial Port 0, chip select 1 (active low)

SSP0_CSZ_2

AC3

Synchronous Serial Port 0, chip select 2 (active low)

UART0_TXD

AB3

UART0 transmit data output

UART0_RXD

AD1

UART0 receive data input

UART0_RTSZ

AD2

UART0 ready to send hardware flow control output (active low)

UART0_CTSZ

AE2

UART0 clear to send hardware flow control input (active low)

USB_DAT_N

USB D- I/O

USB_DAT_P

USB D+ I/O

PMD_INTZ

AE8

Interrupt from DLPA100 (active low). This signal requires an external pull-up. Uses

hysteresis.

CW_PWM

AD8

Color wheel control PWM output

CW_INDEX

AF7

Color wheel index. Uses hysteresis.

LMPCTRL

AC9

Lamp control output. Lamp enable and synchronization to the ballast.

LMPSTAT

AF8

Lamp status input. Driven high from the ballast once the lamp is lit.

DLPC4422 Datasheet(PDF) 9 Page - Texas Instruments

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