DP8418 datasheet(18/28 Pages) NSC

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Applications

If one desires a memory interface containing the DP8419

that minimizes the number of external components required

modes 5 and 1 should be used These two modes provide

1) Automatic access to memory (in mode 5 only one signal

RASIN is required in order to access memory)

2) Hidden refresh capability (refreshes are performed auto-

matically while in mode 5 when non-local accesses are

taking place as determined by CS)

3) Refresh request capability (if no hidden refresh took

place while RFCK was high a refresh request is generat-

ed at the RFIO pin when RFCK goes high)

4) Automatic forced refresh (If a refresh request is generat-

ed while in mode 5 as described above external logic

should switch the DP8419 into mode 1 to do an automat-

ic forced refresh No other external control signals need

be issued WAIT states can be inserted into the proces-

sor machine cycles if the system tries to access memory

while the DP8419 is in mode 1 doing a forced refresh)

Some items to be considered when integrating the DP8419

into a system design are

1) The system designer should ensure that a DRAM access

not be in progress when a refresh mode is entered Simi-

larly one should not attempt to start an access while a

refresh is in progress The parameter tRFHRL specifies

the minimum time from RFSH high to RASIN going low to

initiate an access

2) One should always guarantee that the DP8419 is enabled

for access prior to initiating the access (see tCSRL1)

3) One should bring RASIN low even during non-local ac-

cess cycles when in mode 5 in order to maximize the

chance of a hidden refresh occurring

4) At lower frequencies (under 10 Mhz) it becomes increas-

ingly important to differentiate between READ and

WRITE cycles RASIN generation during READ cycles

can take place as soon as one knows that a processor

READ access cycle has started WRITE cycles on the

other hand cannot start until one knows that the data to

be written at the DRAM inputs will be valid a setup time

before CAS (column address strobe) goes true at the

DRAM inputs Therefore in general READ cycles can be

initiated earlier than WRITE cycles

5) Many times it is possible to only add WAIT states during

READ cycles and have no WAIT states during WRITE

cycles This is because it generally takes less time to

write data into memory than to read data from memory

The DP84XX2 family of inexpensive preprogrammed medi-

um Programmable Array Logic devices (PALs) have been

developed to provide an easy interface between various

microprocessors and the DP84XX family of DRAM control-

lerdrivers These PALs interface to all the necessary con-

trol signals of the particular processor and the DP8419 The

PAL controls the operation of the DP8419 in modes 5 and 1

while meeting all the critical timing considerations discussed

above The refresh clock RFCK may be divided down from

the processor clock using an IC counter such as the

DM74LS393 or the DP84300 programmable refresh timer

The DP84300 can provide RFCK periods ranging from

154 ms to 156 ms based on an input clock of 2 to 10 MHz

Figure 8 shows a general block diagram for a system using

the DP8419 in modes 1 and 5

Figure 9 shows possible

timing diagrams for such a system (using WAIT to prohibit

access when refreshing) Although the DP84XX2 PALs are

offered as standard peripheral devices for the DP84XX

DRAM controllerdrivers the programming equations for

these devices are provided so the user may make minor

modification for unique system requirements

ADVANTAGES OF DP8419 OVER

A DISCRETE DYNAMIC RAM CONTROLLER

1) The DP8419 system solution takes up much less board

space because everything is on one chip (latches re-

fresh counter control logic multiplexers drivers and in-

ternal delay lines)

2) Less effort is needed to design a memory system The

DP8419 has automatic modes (1 and 5) which require a

minimum of external control logic Also programmable ar-

ray logic devices (PALs) have been designed which allow

an easy interface to most popular microprocessors (Mo-

torola 68000 family National Semiconductor 32032 fami-

ly Intel 8086 family and the Zilog Z8000 family)

3) Less skew in memory timing parameters because all crit-

ical components are on one chip (many discrete drivers

specify a minimum on-chip skew under worst-case condi-

tions but this cannot be used if more then one driver is

needed such as would be the case in driving a large

dynamic RAM array)

4) Our switching characteristics give the designer the critical

timing specifications based on TTL output levels (low e

08V high e 24V) at a specified load capacitance All

timing parameters are specified on the DP8419

A) driving 88 DRAM’s over a temperature range of 0 – 70

degrees centigrade (no extra drivers are needed)

B) under worst-case driving conditions with all outputs

switching simultaneously (most discrete drivers on the

market specify worst-case conditions with only one

output switching at a time this is not a true worst-case

condition)

DP8418 Datasheet(PDF) 18 Page - National Semiconductor (TI)

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