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DP8418 Datasheet(PDF) 22 Page - National Semiconductor (TI) |
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DP8418 Datasheet(HTML) 22 Page - National Semiconductor (TI) |
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22 / 28 page  Switching Characteristics DP8417 DP8418 DP8419 DP8419X (Continued) VCC e 50V g10% 0 C s TA s 70 C unless otherwise noted (Notes 2 4 5) The output load capacitance is typical for 4 banks of 22 DRAMs each or 88 DRAMs including trace capacitance These values are Q0-Q8 CL e 500 pF RAS0–RAS3 CL e 150 pF WE CL e 500 pF CAS CL e 600 pF RL e 500X unless otherwise noted See Figure 11a for test load S1 is open unless otherwise specified Maximum propagation delays are specified with all outputs switching Preliminary Symbol Parameter Condition CL All CL e 50 pF Units Min Max Min Max ACCESS (Continued) tRCV0 RASIN to Column Address Figure 6 94 ns Valid (RAHS e 0 Mode 5) DP8417 18 19-80 tRCV0 RASIN to Column Address Figure 6 85 ns Valid (RAHS e 0 Mode 5) DP8417 18 19-70 tRCV1 RASIN to Column Address Figure 6 76 ns Valid (RAHS e 1 Mode 5) DP8417 18 19-80 tRCV1 RASIN to Column Address Figure 6 68 ns Valid (RAHS e 1 Mode 5) DP8417 18 19-70 tRPDL RASIN to RAS Low Delay Figures 5a 5b 6 21 18 ns tRPDH RASIN to RAS High Delay Figures 5a 5b 6 20 17 ns tASRL Address Set-up to RASIN low Figures 5a 5b 6 13 ns tAPD Address Input to Output Figures 5a 5b 6 36 25 ns Delay tSPD Address Strobe High to Figures 5a 5b 48 ns Address Output Valid tASA Address Set-up Time to ADS Figures 5a 5b 6 5ns tAHA Address Hold Time from ADS Figures 5a 5b 6 10 ns tADS Address Strobe Pulse Width Figures 5a 5b 6 26 ns tWPD WIN to WE Output Delay Figure 5b 28 ns tCPDL CASIN to CAS Low Delay Figure 5b 17 33 ns (RC low Mode 4) tCPDH CASIN to CAS High Delay Figure 5b 13 33 ns (RC low Mode 4) tCPdif tCPDL -tCPDH See Mode 4 13 ns Description tRCC Column Select to Column Figure 5a 41 ns Address Valid tRCR Row Select to Row Figures 5a 5b 45 ns Address Valid tRHA Row Address Held from Figure 5a 7ns Column Select tCCAS RC Low to CAS Low Delay Figure 5a 50 ns (CASIN Low Mode 4) DP8417 18 19-80 t RC Low to CAS Low Delay Figure 5a 46 ns (CASIN Low Mode 4) DP8417 18 19-70 tDIF1 Maximum (tRPDL -tRHA) See Mode 4 7ns Description tDIF2 Maximum (tRCC -tCPDL)13 ns REFRESH tRC Refresh Cycle Period Figure 2a 100 ns tRASINLH Pulse Width of RASIN Figure 2a 50 ns during Refresh tRFPDL0 RASIN to RAS Low Delay Figure 2a 28 ns during Refresh (Mode 0) 22 |
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