DP8418 datasheet(23/28 Pages) NSC

23 / 28 page

Switching Characteristics DP8417 DP8418 DP8419 DP8419X (Continued)

VCC e 50V g10% 0 C s TA s 70 C unless otherwise noted (Notes 2 4 5) The output load capacitance is typical for 4 banks

of 22 DRAMs each or 88 DRAMs including trace capacitance

These values are Q0-Q8 CL e 500 pF RAS0–RAS3 CL e 150 pF WE CL e 500 pF CAS CL e 600 pF RL e 500X

unless otherwise noted See

Figure 11a for test load S1 is open unless otherwise specified Maximum propagation

delays are specified with all outputs switching

Symbol

Parameter

Condition

All CL e 50 pF

Units

Min

Max

Min

Max

REFRESH

(Continued)

tRFPDL5

RASIN to RAS Low Delay

Figure 7

during Hidden Refresh

tRFPDH0

RASIN to RAS High Delay

Figure 2a

during Refresh (Mode 0)

tRFPDH5

RASIN to RAS High Delay

Figure 7

during Hidden Refresh

tRFLCT

RFSH Low to Counter

Figures 2a 3

Address Valid

CS e X

tRFLRL

RFSH Low Set-up to RASIN

Figure 2a

Low (Mode 0) to get

Minimum tASR e 0

tRFHRL

RFSH High Setup to Access

Figure 3

RASIN Low

tRFHRV

RFSH High to Row

Figure 3

Address Valid

tROHNC

RAS High to New Count

Figure 2a

Valid

tRST

Counter Reset Pulse Width

Figure 2a

tCTL

RFIO Low to Counter

Figure 2a

100

Outputs All Low

tRFCKLH

Minimum Pulse Width

Figure 7

100

of RFCK

Period of RAS Generator

Figure 3

Clock

tRGCKL

Minimum Pulse Width Low

Figure 3

of RGCK

tRGCKH

Minimum Pulse Width High

Figure 3

of RGCK

tFRQL

RFCK Low to Forced RFRQ

Figure 3

(RFIO) Low

CL e 50 pF

RL e 35k

tFRQH

RGCK Low to Forced RFRQ

Figure 3

High

CL e 50 pF

RL e 35k

tRGRL

RGCK Low to RAS Low

Figure 3

tRGRH

RGCK Low to RAS High

Figure 3

DP8418 Datasheet(PDF) 23 Page - National Semiconductor (TI)

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