DP8418 datasheet(11/28 Pages) NSC

11 / 28 page

DP8419 Mode Descriptions (Continued)

MODE 1 – AUTOMATIC FORCED REFRESH

In Mode 1 the RC (RFCK) pin becomes RFCK (refresh

cycle clock) and the CASIN (RGCK) pin becomes RGCK

(RAS generator clock) If RFCK is high and Mode 1 is en-

tered then the chip operates as if in MODE 0 (externally

controlled refresh) with all RAS outputs following RASIN

This feature of Mode 1 may be useful for those who want to

use Mode 5 (automatic access) with externally controlled

refresh By holding RFCK permanently high one need only

toggle M2 (RFSH) to switch from Mode 5 to external re-

fresh As with Mode 0 RFIO may be pulled low by an ex-

ternal gate to reset the refresh counter

When using Mode 1 as automatic refresh RFCK must be an

input clock signal One refresh should occur each period of

RFCK If no refresh is performed while RFCK is high then

when RFCK goes low RFIO immediately goes low to indi-

cate that a refresh is requested (RFIO may still be used to

reset the refresh counter even though it is also used as a

refresh request pin however an open-collector gate should

be used to reset the counter in this case since RFIO is

forced low internally for a request)

After receiving the refresh request the system must allow a

forced refresh to take place while RFCK is low External

logic can monitor RFRQ (RFIO) so that when RFRQ goes

low this logic will wait for the access currently in progress to

be completed before pulling M2 (RFSH) low to put the

DP8419 in mode 1 If no access is taking place when RFRQ

occurs then M2 may immediately go low Once M2 is low

the refresh counter contents appear at the address outputs

and RAS is generated to perform the refresh

An external clock on RGCK is required to derive the refresh

RAS signals On the second falling edge of RGCK after M2

is low all RAS lines go low They remain low until two more

falling edges of RGCK Thus RAS remains high for one to

two periods of RGCK after M2 goes low and stays low for

two periods In order to obtain the minimum delay from M2

going low to RAS going low M2 should go low tRFSRG be-

fore the falling edge of RGCK

TLF8396 – 11

RFCK goes low

RFRQ goes low if no hidden refresh

occurred while RFCK was high

Next RASIN starts next access

P acknowledges refresh request

Forced refresh RAS starts after l T

(l tRP)

Forced refresh RAS ends RFRQ

P removes refresh acknowledge

FIGURE 3 DP8419 Performing a Forced Refresh (Mode 5

x1x5) with Various Microprocessors

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