X96012 datasheet(6/27 Pages) INTERSIL

6 / 27 page

FN8216.0

March 10, 2005

D/A CONVERTER CHARACTERISTICS (See pg. 4 for Standard Conditions)

Notes: 1.

DAC input Byte = FFh, Source or sink mode.

LSB is defined as

divided by the resistance between R1 or R2 to Vss.

OffsetDAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is

expressed in LSB.

FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It

is expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC.

DNLDAC: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in

the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset

and Full Scale Error before calculating DNLDAC.

INLDAC: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust-

ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.

These parameters are periodically sampled and not 100% tested.

V(I1) and V(I2) are VCC - 1.2V in source mode and 1.2V in sink mode. In this range the current at I1 or I2 varies < 1%.

The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum VCC = 4.5V. The compliance

voltage changes to 2.5V from the sourcing rail, and the current variation is < 1%.

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions / Notes

IFS00

I1 or I2 full scale current, with external

resistor setting

1.56

1.58

1.6

See note 1, 5

3.2

See note 1, 4, 6

IFS01

I1 or I2 full scale current, with internal

low current setting option

0.3

0.4

0.5

DAC input Byte = FFh,

Source or sink mode, V(I1)

and V(I2) are Vcc - 1.2V in

source mode and 1.2V in sink

mode.

See notes 2 and 3.

IFS10

I1 or I2 full scale current, with internal

middle current setting option

0.64

0.85

1.06

IFS11

I1 or I2 full scale current, with internal

high current setting option

11.3

1.6

OffsetDAC

I1 or I2 D/A converter offset error

LSB

FSErrorDAC

I1 or I2 D/A converter full scale error

-2

LSB

DNLDAC

I1 or I2 D/A converter

Differential Nonlinearity

-0.5

0.5

LSB

INLDAC

I1 or I2 D/A converter Integral Nonlin-

earity with respect to a straight line

through 0 and the full scale value

-1

LSB

VISink

I1 or I2 Sink Voltage Compliance

1.2

Vcc

See note 5

2.5

Vcc

See note 4, 6

VISource

I1 or I2 Source Voltage Compliance

Vcc-1.2

See note 5

Vcc-2.5

See note 4, 6

IOVER

I1 or I2 overshoot on D/A Converter

data byte transition

µA

DAC input byte changing from

00h to FFh and vice

versa, V(I1) and V(I2) are

Vcc - 1.2V in source mode

and 1.2V in sink mode.

See note 4.

IUNDER

I1 or I2 undershoot on D/A Converter

data byte transition

µA

trDAC

I1 or I2 rise time on D/A Converter data

byte transition; 10% to 90%

530

µs

TCOI1I2

Temperataure coefficient of output

current I1 or I2 when using internal

resistor setting

±200

ppm/

°C

See Figure 8.

Bits I1FSO[1:0] ¦ 002 or

Bits I2FSO[1:0] ¦ 002,

VRMbit = “1”

V(VRef)

255

[]

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