X96012 datasheet(22/27 Pages) INTERSIL

22 / 27 page

FN8216.0

March 10, 2005

X96012 Memory Map

The X96012 contains a 2176 bit array of mixed volatile

and nonvolatile memory. This array is split up into four

distinct parts, namely: (Refer to figure 15.)

– General Purpose Memory (GPM)

– Look-up Table 1 (LUT1)

– Look-up Table 2 (LUT2)

– Control and Status Registers

The GPM is all nonvolatile EEPROM, located at mem-

ory addresses 00h to 7Fh.

Figure 15. X96012 Memory Map

The Control and Status registers of the X96012 are

used in the test and setup of the device in a system.

These registers are realized as a combination of both

volatile and nonvolatile memory. These registers

reside in the memory locations 80h through 8Fh. The

reserved bits within registers 80h through 86h, must

be written as “0” if writing to them, and should be

ignored when reading. The reserved registers, from

88h through 8Fh, must not be written, and their con-

tent should be ignored.

Both look-up tables LUT1 and LUT2 are realized as

nonvolatile EEPROM, and extend from memory loca-

tions 90h - CFh and D0h - 10Fh respectively. These

look-up tables are dedicated to storing data solely for

the purpose of setting the outputs of Current Genera-

tors I1 and I2 respectively.

All bits in both look-up tables are preprogrammed to

“0” at the factory.

Addressing Protocol Overview

All Serial Interface operations must begin with a

START, followed by a Slave Address Byte. The Slave

address selects the X96012, and specifies if a Read or

Write operation is to be performed.

It should be noted that the Write Enable Latch (WEL)

bit must first be set in order to perform a Write opera-

tion to any other bit. (See “WEL: Write Enable Latch

(Volatile)” on page 14.) Also, all communication to the

X96012 over the 2-wire serial bus is conducted by

sending the MSB of each byte of data first.

Even though the 2176 bit memory consists of four dif-

fering functions, it is physically realized as one contig-

uous array, organized as 17 pages of 16 bytes each.

The X96012 2-wire protocol provides one address

byte, therefore, only 256 bytes can be addressed

directly. The next few sections explain how to access

the different areas for reading and writing.

Figure 16. Slave Address (SA) Format

Look-up Table 2

(LUT2)

Address

Size

64 Bytes

16 Bytes

128 Bytes

10Fh

00h

7Fh

80h

8Fh

90h

CFh

D0h

FFh

Look-up Table 1

(LUT1)

Control & Status

Registers

General Purpose

Memory (GPM)

SA6

SA7

SA5

SA3

SA2

SA1

SA0

Device Type

Identifier

Read or

SA4

Slave Address

Bit(s)

Description

SA7 - SA4

Device Type Identifier

SA3 - SA1

Device Address

SA0

Read or Write Operation Select

R/W

Address

Device

AS0

AS1

AS2

Write

X96012

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