8

FN8216.0

March 10, 2005

2-WIRE INTERFACE A.C. CHARACTERISTICS

2-WIRE INTERFACE TEST CONDITIONS

NONVOLATILE WRITE CYCLE TIMING

Notes: 1.

Cb = total capacitance of one bus line (SDA or SCL) in pF.

2.

is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

3.

The minimum frequency requirement applies between a START and a STOP condition.

4.

These parameters are periodically sampled and not 100% tested.

Symbol

Parameter

Min

Typ

Max

Units

Test Conditions / Notes

SCL Clock Frequency

400

kHz

See “2-Wire Interface Test

Conditions” (below),

See Figure 1, Figure 2 and

Figure 3.

Pulse width Suppression Time at

inputs

50

ns

SCL Low to SDA Data Out Valid

900

ns

Time the bus free before start of new

transmission

1300

ns

Clock Low Time

1.3

µs

Clock High Time

0.6

µs

Start Condition Setup Time

600

ns

Start Condition Hold Time

600

ns

Data In Setup Time

100

ns

Data In Hold Time

0

µs

Stop Condition Setup Time

600

ns

Data Output Hold Time

50

ns

SDA and SCL Rise Time

20

300

ns

SDA and SCL Fall Time

20

300

ns

WP Setup Time

600

ns

WP Hold Time

600

ns

Capacitive load for each bus line

400

pF

Input Pulse Levels

10 % to 90 % of Vcc

Input Rise and Fall Times, between 10% and 90%

10 ns

Input and Output Timing Threshold Level

1.4V

External Load at pin SDA

2.3k

Ω to Vcc and 100 pF to Vss

Symbol

Parameter

Min

Typ

Max

Units

Test Conditions / Notes

Nonvolatile Write Cycle Time

5

10

ms

See Figure 3

X96012