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ML9352 Datasheet(PDF) 21 Page - OKI electronic componets |
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ML9352 Datasheet(HTML) 21 Page - OKI electronic componets |
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21 / 53 page ![]() PEDL9352-01 OKI Semiconductor ML9352 21/53 Display timing generator circuit This circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit and is output to the anode driver output pin in synchronization with the display clock. The read out of the display data to the organic EL drive circuits is completely independent of the display data RAM access from the MPU. As a result, there is no bad influence such as flickering on the display even when the display data RAM is accessed asynchronously during the organic EL display. Also, the internal cathode timing is generated by this circuit from the display clock. Common output state selection circuit (see Table 5) Since the COM output scanning directions can be set using the common output scan direction select command in the ML9352, it is possible to reduce the IC placement restrictions at the time of assembling organic EL modules. Table 5 State COM Scanning direction Normal Display COM0 → COM31 Reverse Display COM31 → COM0 * When the number of display lines is 32. Organic EL Drive circuits The anode driver circuit employs the constant current system and the cathode driver circuit employs the push-pull system. The anode output current is set by the voltage applied to VEL pin, or output voltage of the built-in voltage regulator, and the external resistors connected to the REL1 and REL2 pins. IELA = VEL/REL (Here, IELA: Anode output current; VEL: Voltage applied to VEL pin or the output voltage of built-in voltage regulator; and REL: External resistors connected to the REL1 and REL2 pins.) Selection between the voltage applied to the VEL pin and the output voltage of built-in voltage regulator is by the ELSEL pin. Similarly, selection of REL1 pin or REL2 pin is by the external resistor switching command for adjusting anode output current. When in the power save mode, all operations of the built-in voltage regulator and the organic EL drive circuits are stopped. And the anode and cathode drivers’ outputs go to the VSS level. |
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