ML9352 datasheet(45/53 Pages) OKI

45 / 53 page

PEDL9352-01

OKI Semiconductor

ML9352

45/53

(VDDA = VDDL = 2.7 to 4.5 V, VSSA = VSSL = 0 V, Tjop = –40 to +125°C)

Parameter

Symbol

Condition

Min.

Max.

Unit

Address hold time

Address setup time

tAH8

tAW8

—

System cycle time

tCYC8

400

—

Control “L” pulse width (

WR)

Control “L” pulse width (

RD)

Control “H” pulse width (

WR)

Control “H” pulse width (

RD)

tCCLW

tCCLR

tCCHW

tCCHR

120

—

Data setup time

Data hold time

tDS8

tDH8

—

RD access time

Output disable time

tACC8

tOH8

CL = 100 pF

—

140

100

Note 1:

The input signal rise and fall times are specified as 15 ns or less.

When using the system cycle time for fast speed, the specified values are (tr + tf)

≤ (t

CYC8 –

tCCLW – tCCHW) or (tr + tf) ≤ (tCYC8 – tCCLR – tCCHR).

Note 2:

All timings are specified taking the levels of 20% and 80% of VDD as the reference.

Note 3:

The values of tCCLW and tCCLR are specified during the overlapping period of CS1 at “L” (CS2 =

“H”) and the “L” levels of

WR and RD, respectively.

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