TLE8110ED datasheet(49/74 Pages) INFINEON

49 / 74 page

Data Sheet

Rev. 1.0

2018-03-07

TLE8110ED

Smart Multichannel Low Side Switch with Parallel Control and SPI Interface

Control of the device

8 bits have been counted, the data frame is ignored and a Communication Error is indicated in the CMD_RSDS

- Feedback (see Chapter 12.3.1.2).

12.3

This chapter describes the Registers and Commands. The commands allow to carry through some actions,

such as reading out or clearing the diagnosis or reading out the Input Pins.

Specially highlighted here should be the encoded CMD_DMSx/OPSx commands - compactCONTROL -, a highly

efficient command-set to set a part of the output pins and read out the diagnosis at the same time. Included

in this command set is the possibility to check, if the communication works well as also the possibility to read-

out some of the parallel Input Pins INx. Using this compact command set can reduce the workload of the

micro-controller during run-time significantly.

CMD_RSD is preformed and short diagnostics [SD] is returned after each Write Cycle to any of the writable

registers.

After start-up of the device, the registers are loaded with the default settings as described below in the register

descriptions. The Registers are cleared and set back to the default values, when a low signal is applied to the

pin RST or an under-voltage condition appears at the supply pin VCC what causes an under-voltage reset. If a

low signal at pin EN is applied or an under-voltage condition appears at pin VDD, the Registers are not cleared.

Table 15

Command Overview

Name

Type

Addr.

Short Description

see:

CMD

W 1)

1) if a read command is sent, the command is ignored and S_SO returns a frame with ’0’.

000B

Commands

Chapter 12.3.1

DCC

W 1)

001B

Diagnosis Registers and Compact Control

Chapter 12.3.2

OUTx

W/R

010B

Output Control Register CHx

Chapter 12.3.3

DEVS

W/R

011B

Device Settings

Chapter 12.3.6

MSCS

W/R

100B

Reserved

ISAx

W/R

101B

Input or Serial Mode Register CHx Bank A

Chapter 12.3.4

ISBx

W/R

110B

Input or Serial Mode Register CHx Bank B

Chapter 12.3.4

PMx

W/R

111B

Parallel Mode Control of CHx with CHy

Chapter 12.3.5

Table 16

Nam

Addr

876

321

0def.

CMD W 2)

000B 011

1Command

DCC

W 2)

001B Command

OUTx W/R 010B 11OUT

OUT

C00H

DEVS W/R 011B RCP DBT2 DBT1 000

0DCC

DCC

007H

MSCS W/R 100B Reserved

000H

ISAx

W/R 101B IS6

IS5

IS4

IS3

IS2

IS1

AAAH

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