TLV9352IDDFR datasheet(8/52 Pages) TI

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6.7 Electrical Characteristics

For VS = (V+) – (V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS /

2, and VO UT = VS / 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

VOS

Input offset voltage

VCM = V–

±0.35

±1.8

TA = –40°C to 125°C

±2

dVOS/dT

Input offset voltage drift

TA = –40°C to 125°C

±1.5

µV/

℃

PSRR

Input offset voltage

versus power supply

VCM = V–

TA = –40°C to 125°C

±2

±5

μV/V

Channel separation

f = 0 Hz

µV/V

INPUT BIAS CURRENT

Input bias current

±10

IOS

Input offset current

±10

NOISE

Input voltage noise

f = 0.1 Hz to 10 Hz

μVPP

0.33

µVRMS

Input voltage noise

density

f = 1 kHz

nV/√ Hz

f = 10 kHz

Input current noise

f = 1 kHz

fA/√ Hz

INPUT VOLTAGE RANGE

VCM

Common-mode voltage

range

(V–) – 0.2

(V+) – 2

CMRR

Common-mode rejection

ratio

VS = 40 V, (V–) – 0.1 V < VCM < (V+)

– 2 V (Main input pair)

TA = –40°C to 125°C

110

VS = 4.5 V, (V–) – 0.1 V < VCM < (V

+) – 2 V (Main input pair)

INPUT CAPACITANCE

ZID

Differential

100 || 3

MΩ || pF

ZICM

Common-mode

6 || 1

TΩ || pF

OPEN-LOOP GAIN

AOL

Open-loop voltage gain

VS = 40 V, VCM = V–

(V–) + 0.1 V < VO < (V+) – 0.1 V

120

130

TA = –40°C to 125°C

116

127

TLV9352

SBOS994B – NOVEMBER 2019 – REVISED AUGUST 2020

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