MAS3504D datasheet(6/40 Pages) MICRONAS

6 / 40 page

MAS 3504D

Micronas

2. Functional Description

2.1. DSP Core

The hardware of the MAS 3504D consists of a high

performance Digital Signal Processor and appropriate

interfaces. The processor works with a memory word

length of 20 bits and an extended range of 32 bits in its

accumulators. The instruction set of the DSP is highly

optimized for audio data compression and decompres-

sion. Thus, only very small areas of internal RAM and

ROM are required. All data input and output actions

are based on a ‘non cycle stealing’ background DMA

that does not cause any computational overhead.

2.2. Firmware (Internal Program ROM)

The firmware fully contains a G.729 voice decoder.

With an additional support routine the IC is extended to

a G.729 Annex A encoder.

The G.729 standard compresses 8 kHz/16 bit mono

voice data in frames of 80 samples to 10 bytes each,

what results in a compressed bitstream of 1 bit/sam-

ple. The encoding according to Annex A has reduced

complexity, but is fully compatible to the initial G.729

standard. Therefore the MAS 3504D can decode bit-

streams that were encoded by other G.729 encoders

and it can encode bitstreams that can be decoded with

other G.729 decoders.

2.2.1. G.729 Encoder

For encoding operation the MAS 3504D has to be pre-

pared by downloading an additional routine to support

the encoder. After starting the encoder, 80 audio sam-

ples are continuously read via the serial input inter-

face. Each audio block of 80 samples is encoded to a

G.729 data frame consisting of 10 bytes which is sent

via the parallel interface. It is possible to monitor the

input audio samples also directly via the serial output

interface.

2.2.2. G.729 Decoder

The MAS 3504D expects a sequence of valid G.729

frames (10 bytes each) as input. The compressed data

is sent via the parallel interface. Each frame is

decoded to 80 audio samples, modified by the volume/

mute control and sent out via the serial output inter-

face.

2.3. Program Download Feature

The overall function of the MAS 3504D can be altered

by downloading up to 1 kWord program code into the

internal RAM and by executing this code instead of the

ROM code. During this time, G.729 processing is not

possible.

The code must be downloaded by the ‘write to mem-

ory’ command (see Section 3.3. on page 14) into an

area of internal RAM. A ‘run’ command starts the oper-

ation.

Micronas provides modules for encoding and decoding

audio data with ADPCM.

Detailed information about downloading is provided in

combination with the MAS 3504D software develop-

ment package from Micronas.

2.4. Clock Management

The MAS 3504D should be driven by a single clock at

a frequency of 18.432 MHz.

The CLKI signal acts as a reference for the embedded

clock synthesizer that generates the internal system

clock.

2.5. Power Supply Concept

The MAS 3504D offers an embedded controlled DC/

DC converter and voltage monitoring circuits for bat-

tery based power supply concepts. It works as an up-

converter. The application circuit for the DC/DC con-

verter is shown in Fig. 2–1.

2.5.1. Internal Voltage Monitor

An internal voltage monitor compares the input voltage

at the VSENS pin with an internal reference value that

is adjustable via I2C bus. The PUP output pin becomes

inactive when the voltage at the VSENS pin drops

below the programmed value of the reference voltage.

It is important that the WSEN must not be activated

before the PUP is generated. The PUP signal thresh-

olds are listed in Table 3–8 on page 19.

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