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TAS2764YBHT Datasheet(PDF) 32 Page - Texas Instruments |
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TAS2764YBHT Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 107 page  Table 8-5. Fault Interrupt Mask (continued) Interrupt Live Register Latch Register Mask Register Default (1 = Mask) PVDD-VBAT1S Below Threshold IL_PVBT IR_PVBT IM_PVBT 0 Internal VBAT1S LDO Over Voltage Device in shutdown IR_LDO_OV IM_LDO_OV 1 Internal VBAT1S LDO Under Voltage Device in shutdown IR_LDO_UV IM_LDO_UV 0 Internal VBAT1S LDO Over Load Device in shutdown IR_LDO_OL IM_LDO_OL 1 8.6.1 Faults and Status over TDM Faults and device operation information can be sent over the TDM bus when STATUS_TX register bit is set high. The slot position in TDM bus can be configured using STATUS_SLOT[5:0] register bits. Table 8-6. TDM Information Bits TDM_STATUS[7:0] Bit Bit Information 0 Value 1 Value 0 Power up state Powered down(1) Powered up 1 Y-Bridge PVDD active VBAT1S active 2 Noise-Gate Status Normal operation Noise gate active 3 Limiter Active No Limiter or ICLA attn applied Limiter or ICLA attn applied 4 BOP Active No BOP attn applied BOP attn applied 5 Over Temperature Error No Over-temperature Over-temperature detected(1) 6 Over Current Error No Over-current Over-current detected(1) 7 PVDD Status No PVDD UVLO PVDD UVLO detected(1) (1) Can be read only during the transient shutdown phase. After shutdown the TDM slots are not available. 8.7 Power Sequencing Requirements There are no power sequencing requirements for order of the supplies other than PVDD and VBAT1S. During power up and power down PVDD voltage must be greater than (VBAT1S-0.7V). 8.8 Digital Input Pull Downs Each digital input and IO has an optional weak pull down to prevent the pin from floating. Register bits DIN_PD[4:0] are used to enable/disable pull downs. The pull downs are not enabled during HW shutdown. 8.9 Register Map 8.9.1 Register Summary Table Page=0x00 Addr Register Description Section 0x00 PAGE Device Page Section 8.9.5 0x01 SW_RESET Software Reset Section 8.9.6 0x02 MODE_CTRL Device operational mode Section 8.9.7 0x03 CHNL_0 Y Bridge and Channel settings Section 8.9.8 0x04 DC_BLK0 SAR Filter and DC Path Blocker Section 8.9.9 0x05 DC_BLK1 ERC and Record DC Blocke Section 8.9.10 0x06 MISC_CFG1 Misc Configuration 1 Section 8.9.11 0x07 MISC_CFG2 Misc Configuration 2 Section 8.9.12 0x08 TDM_CFG0 TDM Configuration 0 Section 8.9.13 0x09 TDM_CFG1 TDM Configuration 1 Section 8.9.14 0x0A TDM_CFG2 TDM Configuration 2 Section 8.9.15 0x0B LIM_MAX_ATTN Limiter Section 8.9.16 0x0C TDM_CFG3 TDM Configuration 3 Section 8.9.17 0x0D TDM_CFG4 TDM Configuration 4 Section 8.9.18 0x0E TDM_CFG5 TDM Configuration 5 Section 8.9.19 0x0F TDM_CFG6 TDM Configuration 6 Section 8.9.20 TAS2764 SLOS998 – DECEMBER 2020 www.ti.com 32 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TAS2764 |
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