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TAS2764YBHT Datasheet(PDF) 97 Page - Texas Instruments |
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TAS2764YBHT Datasheet(HTML) 97 Page - Texas Instruments |
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97 / 107 page ![]() If VBAT1S is generated by internal LDO, customer needs to ensure that PVDD supply level is at least 2.5V above the VBAT1S voltage generated internally. To enable Y-Bridge configuration protection the UVLO of PVDD supply should be set above 7.3V by using register bits PVDD_UVLO[5:0]. This will ensure that, with an internally generated VBAT1S of 4.8V, PVDD supply is at least 2.5V higher than VBAT1S and Y-Bridge configuration can function properly. www.ti.com TAS2764 SLOS998 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 97 Product Folder Links: TAS2764 |
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