TAS2764YBHT datasheet(18/107 Pages) TI

18 / 107 page

8-BitDatafor

Figure 8-1. Typical I2C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus. Figure 8-1 shows a generic data

transfer sequence.

For information about pull-up resistors and single-byte/multiple-byte transfers see Section 11.

8.3.3 Register Organization

Device configuration and coefficients are stored using a page and book scheme. Each page contains 128 bytes

and each book contains 256 pages. All device configuration registers are stored in book 0, page 0, which is the

default setting at power up (and after a software reset). The book and page can be set by the BOOK and PAGE

registers respectively.

Note

Programming register bits from Book_0 and Page_4 needs to be done in groups of four registers (32

bit format), each byte corresponding to a register and with less significant byte programmed to 00h.

For instance, when programing DC level for diagnostic generator, registers 08,09,0A will be

programmed to the desired value and register 0B will be programmed to 00h.

8.4 Device Functional Modes

8.4.1 TDM Port

The TAS2764 provides a flexible TDM serial audio port. The port can be configured to support a variety of

formats including stereo I2S, Left Justified and TDM. Mono audio playback is available via the SDIN pin. The

SDOUT pin is used to transmit sample streams including speaker voltage and current sense, PVDD voltage, die

temperature and channel gain.

The TDM serial audio port supports up to 16 of 32-bit time slots at 44.1/48 kHz or 8 of 32-bit time slots at a

88.2/96 kHz sample rate. Valid SBCLK to FSYNC ratios are 16, 24, 32, 48, 64, 96, 128, 192, 256, and 512. The

device will automatically detect the number of time slots and it does not need to be programmed.

By default, the TAS2764 will automatically detect the PCM playback sample rate. This can be disabled and

manually configured by setting the AUTO_RATE register bit high.

The SAMP_RATE[2:0] and SAMP_RATIO[3:0] register bits are used to configure the PCM audio sample rate

when AUTO_RATE register bit is high (auto detection of TDM sample rate is disabled). The TAS2764 employs a

robust clock fault detection engine that will automatically volume ramp down the playback path if FSYNC does

not match the configured sample rate (if AUTO_RATE = 1) or the ratio of SBCLK to FSYNC is not supported

(minimizing any audible artifacts). Once the clocks are detected to be valid in both frequency and ratio, the

device will automatically volume ramp the playback path back to the configured volume and resume playback.

When using the auto rate detection the sampling rate and SBCLK to FSYNC ration detected on the TDM bus is

reported back on the read-only register bits FS_RATE[2:0] and FS_RATIO[3:0] respectively.

The TAS2764 supports a 12 MHz SBCLK operation. The system will detect or should be manually configured for

a ratio of 125 or 250. In this specific ratio the last 32-bit slot should not be used to transmit data over the Section

8.4.1 or Section 8.4.2.9.1 as data will be truncated.

Figure 8-2 and Figure 8-3 below illustrate the receiver frame parameters required to configure the port for

playback. A frame begins with the transition of FSYNC from either high to low or low to high (set by the

FRAME_START register bit). FSYNC and SDIN are sampled by SBCLK using either the rising or falling edge

(set by the RX_EDGE register bit). The RX_OFFSET[4:0] register bits define the number of SBCLK cycles from

TAS2764

SLOS998 – DECEMBER 2020

www.ti.com

Submit Document Feedback

Product Folder Links: TAS2764

TAS2764YBHT Datasheet(PDF) 18 Page - Texas Instruments

TAS2764YBHT Datasheet(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL