INA229 datasheet(25/40 Pages) TI

25 / 40 page

7.6.1.12 Diagnostic Flags and Alert (DIAG_ALRT) Register (Address = Bh) [reset = 0001h]

The DIAG_ALRT register is shown in Table 7-16.

Return to the Summary Table.

Table 7-16. DIAG_ALRT Register Field Descriptions

Bit

Field

Type

Reset

Description

ALATCH

R/W

When the Alert Latch Enable bit is set to Transparent mode, the Alert

pin and Flag bit reset to the idle state when the fault has been

cleared.

When the Alert Latch Enable bit is set to Latch mode, the Alert pin

and Alert Flag bit remain active following a fault until the DIAG_ALRT

0h = Transparent

1h = Latched

CNVR

R/W

Setting this bit high configures the Alert pin to be asserted when the

Conversion Ready Flag (bit 1) is asserted, indicating that a

conversion cycle has completed.

0h = Disable conversion ready flag on ALERT pin

1h = Enables conversion ready flag on ALERT pin

SLOWALERT

R/W

ALERT function is asserted on the completed averaged value.

This gives the flexibility to delay the ALERT after the averaged value.

0h = ALERT comparison on non-averaged (ADC) value

1h = ALERT comparison on Averaged value

APOL

R/W

Alert Polarity bit sets the Alert pin polarity.

0h = Normal (Active-low, open-drain)

1h = Inverted (active-high, open-drain )

ENERGYOF

This bit indicates the health of the ENERGY register.

If the 40 bit ENERGY register has overflowed this bit is set to 1.

0h = Normal

1h = Overflow

Clears when the ENERGY register is read.

CHARGEOF

This bit indicates the health of the CHARGE register.

If the 40 bit CHARGE register has overflowed this bit is set to 1.

0h = Normal

1h = Overflow

Clears when the CHARGE register is read.

MATHOF

This bit is set to 1 if an arithmetic operation resulted in an overflow

error.

It indicates that current and power data may be invalid.

0h = Normal

1h = Overflow

Must be manually cleared by triggering another conversion or by

clearing the accumulators with the RSTACC bit.

RESERVED

Reserved. Always read 0.

TMPOL

R/W

This bit is set to 1 if the temperature measurement exceeds the

threshold limit in the temperature over-limit register.

0h = Normal

1h = Over Temp Event

When ALATCH =1 this bit is cleared by reading the DIAG_ALERT

SHNTOL

R/W

This bit is set to 1 if the shunt voltage measurement exceeds the

threshold limit in the shunt over-limit register.

0h = Normal

1h = Over Shunt Voltage Event

When ALATCH =1 this bit is cleared by reading the register.

SHNTUL

R/W

This bit is set to 1 if the shunt voltage measurement falls below the

threshold limit in the shunt under-limit register.

0h = Normal

1h = Under Shunt Voltage Event

When ALATCH =1 this bit is cleared by reading the register.

www.ti.com

INA229

SLYS023 – DECEMBER 2020

Submit Document Feedback

Product Folder Links: INA229

INA229 Datasheet(PDF) 25 Page - Texas Instruments

INA229 Datasheet(HTML) 25 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL