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AD4680/AD4681

Data Sheet

Rev. 0 | Page 14 of 29

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD4680/AD4681 are high speed, dual simultaneous sampling,

fully differential 16-bit, SAR ADCs. The AD4680/AD4681

operate from a 3.0 V to 3.6 V power supply and feature

throughput rates of 1 MSPS (AD4680) and 500 kSPS (AD4681).

The AD4680/AD4681 contain two SAR ADCs and a serial

interface with two separate data output pins. The device is

housed in a 16-lead LFCSP, offering the user considerable space-

saving advantages over alternative solutions.

Data is accessed from the device via the serial interface. The

interface can operate with one or two serial outputs. The

AD4680/AD4681 have an on-chip, 2.5 V, internal VREF. If an

external reference is desired, the internal reference can be

disabled, and a reference value ranging from 2.5 V to 3.3 V can

be supplied. If the internal reference is used elsewhere in the

system, the reference output must be buffered. The differential

analog input range for the AD4680/AD4681 is the common-

mode voltage (VCM) ± VREF/2.

The AD4680/AD4681 feature on-chip oversampling blocks to

improve performance. Rolling average oversampling mode and

power-down options that allow power saving between

conversions are also available. Configuration of the device is

implemented via the standard serial interface (see the Interface

section).

CONVERTER OPERATION

The AD4680/AD4681 have two SAR ADCs, each based around

two capacitive digital-to-analog converters (DACs). Figure 30

and Figure 31 show simplified schematics of one of the ADCs

in acquisition and conversion phases, respectively. The ADC

comprises control logic, an SAR, and two capacitive DACs. In

Figure 30 (the acquisition phase), SW3 is closed, SW1 and SW2

are in Position A, the comparator is held in a balanced

condition, and the sampling capacitor (CS) arrays can acquire

the differential signal on the input.

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

SW2

VREF

AINx+

AINx–

Figure 30. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 31), SW3 opens

and SW1 and SW2 move to Position B, causing the comparator

to become unbalanced. Both inputs are disconnected when the

conversion begins. The control logic and charge redistribution

DACs are used to add and subtract fixed amounts of charge

from the sampling capacitor arrays to bring the comparator

back into a balanced condition. When the comparator is

rebalanced, the conversion is complete. The control logic

generates the ADC output code. The output impedances of the

sources driving the AINx+ and AINx− pins must be matched.

Otherwise, the two inputs have different settling times,

resulting in errors.

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

SW2

VREF

AINx+

AINx–

Figure 31. ADC Conversion Phase

ANALOG INPUT STRUCTURE

Figure 32 shows the equivalent circuit of the analog input structure

of the AD4680/AD4681. The four diodes (D) provide ESD

protection for the analog inputs. Ensure that the analog input

signals never exceed the supply rails by more than 300 mV.

Exceeding the limit causes these diodes to become forward-

biased and start conducting into the substrate. These diodes can

conduct up to 10 mA without causing irreversible damage to

the device.

The C1 capacitors in Figure 32 are typically 3 pF and can primarily

be attributed to pin capacitance. The R1 resistors are lumped

components made up of the on resistance of the switches. The

value of these resistors is typically about 200 Ω. The C2 capacitors

are the sampling capacitors of the ADC with a capacitance of

15 pF typically.

VCC

R1 C2

VCC

R1 C2

AINx+

AINx–

Figure 32. Equivalent Analog Input Circuit,

Conversion Phase—Switches Open, Track Phase—Switches Closed

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