AD7380 datasheet(18/29 Pages) AD

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AD4680/AD4681

Data Sheet

Rev. 0 | Page 18 of 29

MODES OF OPERATION

The AD4680/AD4681 have several on-chip configuration

registers for controlling the operational mode of the device.

OVERSAMPLING

Oversampling is a common method used in analog electronics

to improve the accuracy of the ADC result. Multiple samples of

the analog input are captured and averaged to reduce the noise

component from quantization noise and thermal noise (kTC)

of the ADC. The AD4680 and the AD4681 offer an

oversampling function on chip, rolling average oversampling.

The rolling average oversampling functionality is enabled by

writing a 1 to the OS_MODE bit and a valid nonzero to the

OSR bits, Bits[8:6] in the CONFIGURATION1 register.

Oversampling can be disabled by writing 0 to OS_MODE and a

zero value to the OSR bits of the CONFIGURATION1 register.

Rolling Average Oversampling

Rolling average oversampling mode can be used in applications

where higher output data rates are required and where higher

SNR or dynamic range is desirable. Rolling averaging involves

taking a number of samples, adding the samples together, and

dividing the result by the number of samples taken. This result

is then output from the device. The sample data is not cleared

after the process is completed. The rolling average oversampling

mode uses a first in, first out (FIFO) buffer of the most recent

samples in the averaging calculation, allowing the ADC

throughput rate and output data rate to stay the same.

The oversampling ratio of the digital filter is controlled using the

oversampling bits, OSR (see Table 10). The output result is

decimated to 16-bit resolution for the AD4680/AD4681. If

additional resolution is required, this resolution can be

achieved by configuring the resolution boost bit, RES, in the

CONFIGURATION1 register. See the Resolution Boost section

for further details.

In rolling average oversampling mode, all ADC conversions are

controlled and initiated by the falling edge of CS. After a

conversion is complete, the result is loaded into the FIFO. The

FIFO length is 8, regardless of the oversampling ratio set. The

FIFO is filled on the first conversion after a power-on reset, the

first conversion after a software controlled hard or soft reset, or

on the first conversion after the REFSEL bit is toggled. A new

conversion result is shifted into the FIFO on completion of

every ADC conversion, regardless of the status of the OSR bits

and the OS_MODE bit. This conversion allows a seamless

transition from no oversampling to rolling average oversampling,

or different rolling average oversampling ratios without waiting

for the FIFO to fill.

The number of samples, n, defined by the OSR bits are taken from

the FIFO, added together, and the result is divided by n. The time

between CS falling edges is the cycle time, which can be controlled

by the user, depending on the desired data output rate.

Table 10. Rolling Average Oversampling Performance Overview

Oversampling

Ratio

AD4680

AD4681

SNR (dB Typical)

Output Data Rate

(kSPS Maximum)

SNR (dB Typical)

Output Data Rate

(kSPS Maximum)

VREF = 2.5 V

VREF = 3.3 V

RES = 0

RES = 1

RES = 0

RES = 1

RES = 0

RES = 1

Disabled

92.5

1000

500

93.2

94.5

1000

84.5

87.7

500

94.8

97.2

1000

500

95.5

98.6

95.9

99.6

1000

85.5

500

INTERNAL

VCC

SDI

SDOA

SDOB/ALERT

ACQ

ENABLE OS = 2

ENABLE OS = 4

DON’T CARE

ACQ

...

FIFO

–

FIFO

–

FIFO

–

FIFO

–

FIFO

–

FIFO

–

FIFO

–

(FIFO1 + FIFO2 +

FIFO3 + FIFO4)/4

(FIFO1 +

FIFO2)/2

(FIFO1 +

FIFO2)/2

(FIFO1 +

FIFO2)/2

Figure 35. Rolling Average Oversampling Operation

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