Data Sheet

AD4680/AD4681

Rev. 0 | Page 25 of 29

REGISTERS

The AD4680/AD4681 have user programmable on-chip registers for configuring the device. Table 13 shows a complete overview of the

registers available on the AD4680/AD4681. The registers are either read/write (R/W) or read only (R). Any read request to a write only

register is ignored. Any write request to a read only register is ignored. Writes to any other register address are considered an NOP and

are ignored. Any read request to a register address, other than those listed in Table 13, are considered an NOP, and the data transmitted

in the next SPI frame are the conversion results.

Table 13. Register Summary

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Hex. No.

Register Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

R/W

0x1

CONFIGURATION1

[15:8]

ADDRESSING

RESERVED

OS_MODE

OSR, Bit 2

0x0000

R/W

[7:0]

OSR, Bits[1:0]

CRC_W

CRC_R

ALERT_EN

RES

REFSEL

PMODE

0x2

CONFIGURATION2

[15:8]

ADDRESSING

RESERVED

SDO

0x0000

R/W

[7:0]

RESET

0x3

ALERT

[15:8]

ADDRESSING

RESERVED

CRCW_F

SETUP_F

0x0000

R

[7:0]

RESERVED

AL_B_HIGH

AL_B_LOW

RESERVED

AL_A_HIGH

AL_A_LOW

0x4

ALERT_LOW_THRESHOLD

[15:8]

ADDRESSING

ALERT_LOW, Bits[11:8]

0x0800

R/W

[7:0]

ALERT_LOW, Bits[7:0]

0x5

ALERT_HIGH_THRESHOLD

[15:8]

ADDRESSING

ALERT_HIGH, Bits[11:8]

0x07FF

R/W

[7:0]

ALERT_HIGH, Bits[7:0]

ADDRESSING REGISTERS

A serial register transfer on the AD4680/AD4681 consists of 16 SCLK cycles. The four MSBs written to the device are decoded to

determine which register is addressed. The four MSBs consist of the register address (REGADDR), Bits[14:12], and the read/write bit

(WR). The register address bits determine which on-chip register is selected. If the addressed register is a valid write register, the

read/write bit determines whether the remaining 12 bits of data on the SDI input are loaded into the addressed register. If the WR bit is

1, the bits load into the register addressed by the register select bits. If the WR bit is 0, the command is seen as a read request. The

addressed register data is available to be read during the next read operation.

Table 14. Addressing Register Format

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

WR

REGADDR

Data

Table 15. Bit Descriptions for Addressing Registers

Bit

Mnemonic

Description

D15

WR

When a 1 is written to this bit, Bits[11:0] of this register are written to the register specified by REGADDR, if it

is a valid address. Alternatively, when a 0 is written, the next data sent out on the SDOA pin is a read from

the designated register if it is a valid address.

D14 to D12

REGADDR

When WR = 1, the contents of REGADDR determine the register for selection as outlined in Table 13.

When WR = 0 and REGADDR contains a valid register address, the contents on the requested register are

output on the SDOA pin during the next interface access.

When WR = 0 and REGADDR contains 0x0, 0x6, or 0x7, the contents on the SDI line are ignored. The next

interface access results in the conversion results being read back.

D11 to D0

Data

These bits are written into the corresponding register specified by the REGADDR bits when the WR bit is

equal to 1 and the REGADDR bits contain a valid address.