AD7380 datasheet(21/29 Pages) AD

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Data Sheet

AD4680/AD4681

Rev. 0 | Page 21 of 29

INTERFACE

The interface to the AD4680/AD4681 is via a serial interface.

The interface consists of the CS, SCLK, SDOA, SDOB/ALERT,

and SDI pins.

The CS signal frames a serial data transfer and initiates an ADC

conversion process. The falling edge of CS puts the track-and-

hold into hold mode, at which point the analog input is sampled,

and the bus is taken out of three-state.

The SCLK signal synchronizes data in and out of the device via

the SDOA, SDOB, and SDI signals. A minimum of 16 SCLK

cycles are required for a write to or read from a register. The

minimum numbers of SCLK cycles for a conversion read is

dependent on the resolution of the device and the configuration

settings (see Table 11).

The ADC conversion operation is driven internally by an on-board

oscillator and is independent of the SCLK signal.

The AD4680/AD4681 have two serial output signals, SDOA

and SDOB. To achieve the highest throughput of the device,

use both SDOA and SDOB, 2-wire mode, to read the

conversion results. If a reduced throughput is required or

oversampling is used, it is possible to use 1-wire mode, the

SDOA signal only, for reading conversion results.

Programming the SDO bit in the CONFIGURATION2 register

configures 2-wire or 1-wire mode.

Configuring the cyclic redundancy check (CRC) operation for

SPI reads or SPI writes alters the operation of the interface.

Consult the relevant CRC Read, CRC Write, and CRC

Polynomial sections to ensure proper operation.

READING CONVERSION RESULTS

The CS signal initiates the conversion process. A high to low

transition on the CS signal initiates a simultaneous conversion

of both ADCs, ADC A and ADC B. The AD4680/AD4681 have

a one-cycle readback latency. Therefore, the conversion results

are available on the next SPI access. Then, take the CS signal

low, and the conversion result clocks out on the serial output

pins. The next conversion is also initiated at this point.

The conversion result is shifted out of the device as a 16-bit

result for the AD4680/AD4681. The MSB of the conversion result

is shifted out on the CS falling edge. The remaining data is

shifted out of the device under the control of the SCLK input.

The data is shifted out on the rising edge of SCLK, and the data

bits are valid on both the falling edge and the rising edge. After

the final SCLK falling edge, take CS high again to return the SDOA

and SDOB/ALERT pins to a high impedance state.

The number of SCLK cycles to propagate the conversion results

on the SDOA and SDOB/ALERT pins is dependent on the serial

mode of operation configured and if resolution boost mode is

enabled (see Figure 39 and Table 11 for details). If CRC reading

is enabled, additional SCLK cycles are required to propagate the

CRC information (see the CRC section for more details).

As the CS signal initiates a conversion, as well as framing the

data, any data access must be completed within a single frame.

Table 11. Number of SCLK Cycles, n, Required for Reading

Conversion Results

Interface

Configuration

Resolution

Boost Mode

CRC

Read

SCLK

Cycles

2-Wire

Disabled

Enabled

Disabled

Enabled

1-Wire

Disabled

Enabled

Disabled

Enabled

n–2

n–1

SCLK

CONVERSION RESULT

1CONSULT TABLE 11 FOR n, THE NUMBER OF SCLK CYCLES REQUIRED

SDOA

SDOB/ALERT

Figure 39. Reading Conversion Result

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