AD9083EBZ datasheet(45/93 Pages) AD

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Data Sheet

AD9083

Rev. 0 | Page 45 of 93

DIGITAL OUTPUTS

The AD9083 digital outputs are designed to the JEDEC standard

JESD204B, serial interface for data converters. JESD204B is a

protocol to link the AD9083 to a digital processing device over

a serial interface with lane rates of up to 16 Gbps. The benefits

of the JESD204B interface over LVDS include a reduction in

required board area for data interface routing, and an ability to

enable smaller packages for converter and logic devices.

JESD204B OVERVIEW

The JESD204B data transmit block assembles the parallel data

from the ADC into frames and uses 8-bit/10-bit encoding as

well as optional scrambling to form serial output data. Lane

synchronization is supported through the use of special control

characters during the initial establishment of the link. Additional

control characters are embedded in the data stream to maintain

synchronization thereafter. A JESD204B receiver is required to

complete the serial link. For additional details on the JESD204B

interface, refer to the JESD204B standard.

The AD9083 JESD204B data transmit block maps up to sixteen

physical ADCs or up to 96 virtual converters (when all the

DDCs are enabled) over a link. A link can be configured to use

one, two, or four JESD204B lanes. The JESD204B specification

refers to a number of parameters to define the link, and these

parameters must match between the JESD204B transmitter (the

AD9083 output) and the JESD204B receiver (the logic device

input).

The JESD204B link is described according to the following

parameters:

•

L is the number of lanes per converter device (lanes per

link); (AD9083 value = 1, 2, 3, or 4)

•

M is the number of converters per converter device

(virtual converters per link) (AD9083 value = 16, 32, 96)

•

F is the octets/frame (AD9083 value = 2, 3, 4, 6, 8, 12, 16,

24, 32, 48, 64, 72 or 96)

•

N΄ is the number of bits per sample (JESD204B word size)

(AD9083 value = 12 or 16)

•

N is the converter resolution

•

CS is the number of control bits/sample

(AD9083 value = 0, 1, 2, or 3)

•

K is the number of frames per multiframe

(AD9083 value = 8, 16, or 32 )

•

S is the samples transmitted/single converter/frame cycle

(AD9083 value = set automatically based on L, M, F, and N΄)

•

HD is the high density mode (AD9083 = set automatically

based on L, M, F, and N΄)

•

CF is the number of control words/frame clock

cycle/converter device (AD9083 value = 0)

Figure 85 shows a simplified block diagram of the AD9083

JESD204B link. The AD9083 can be configured to use

sixteen converters and four lanes. Data from all sixteen

converters is output to SERDOUT0±, SERDOUT1±,

SERDOUT2± and SERDOUT3±. The AD9083 allows other

configurations, such as combining the outputs of all converters

onto a single lane. These modes are customizable, and can be

set up via the SPI.

In the AD9083, if N’ = 16, the N-bit converter word from each

converter is broken into two octets (eight bits of data). Bit N − 1

(MSB) through Bit N-8 are in the first octet. The second octet

contains Bit N − 9 through Bit 0 (LSB), CS control bits (the CS

parameter defines the number of control bits), and tail bits, if

necessary, are appended to the LSB’s to achieve N’ number of

bits in the JESD word. If tail bits are needed, they can be

configured as zeros or a pseudorandom number sequence.

Control bits can be used to indicate overrange, SYSREF±, or

fast detect output.

For modes where N’ = 12, each of the M/L samples on a lane

are concatenated starting with sample 0 on lane 0 to create the

F octets in each lane. If control bits are required, then N must

equal N’ – CS.

The resulting octets can be scrambled. Scrambling is optional;

however, it is recommended to avoid spectral peaks when

transmitting similar digital data patterns. The scrambler uses a

self-synchronizing, polynomial-based algorithm defined by the

equation 1 + x14 + x15. The descrambler in the receiver is a self-

synchronizing version of the scrambler polynomial.

The octets are then encoded with an 8-bit/10-bit encoder. The

8-bit/10-bit encoder works by taking eight bits of data (an

octet) and encoding them into a 10-bit symbol.

LANE MUX

AND

MAPPING

SERDOUT0±

SYSREF±

SYNCINB±

SERDOUT1±

SERDOUT2±

SERDOUT3±

JESD204B

LINK

CONTROL

DSP BLOCK/

FORMAT

ADC 1

ADC 15

INPUT 1

INPUT 15

Figure 85. Transmit Link Simplified Block Diagram

AD9083EBZ Datasheet(PDF) 45 Page - Analog Devices

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