AD9083EBZ datasheet(48/93 Pages) AD

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AD9083

Data Sheet

Rev. 0 | Page 48 of 93

SERDOUTx+

SERDOUTx–

RECEIVER

100Ω

DIFFERENTIAL

TRACE PAIR

OUTPUT SWING = 675mV p-p DIFFERENTIAL

ADJUSTABLE

0.1µF

DVDD

0.1µF

100Ω

Figure 88. AC-Coupled Digital Output Termination Example

PHYSICAL LAYER (DRIVER) OUTPUTS

Digital Outputs, Timing, and Controls

The AD9083 physical layer consists of drivers that are defined in

the JEDEC Standard JESD204B, July 2011. The differential digital

outputs are powered up by default. The drivers use a dynamic

100 Ω internal termination to reduce unwanted reflections.

Place a 100 Ω differential termination resistor at each receiver

input to result in a nominal 0.85 × DVDD V p-p swing at the

receiver (see Figure 88). The swing is adjustable through the

SPI registers. AC coupling is recommended to connect to the

receiver. See the Memory Map section (Register 0x402 to

The AD9083 digital outputs can interface with custom ASICs

and field programmable gate array (FPGA) receivers, providing

superior switching performance in noisy environments. Single

point-to-point network topologies are recommended with a

single differential 100 Ω termination resistor placed as close to

the receiver inputs as possible.

If there is no far end receiver termination, or if there is poor

differential trace routing, timing errors can result. To avoid

such timing errors, it is recommended that the trace length be

less than six inches, and that the differential output traces be

close together and at equal lengths.

The format of the output data is twos complement by default.

To change the output data format, see the Memory Map section

Deemphasis

Deemphasis enables the receiver eye diagram mask to be met in

conditions where the interconnect insertion loss does not meet

the JESD204B specification. Use the deemphasis feature only

when the receiver is unable to recover the clock due to excessive

insertion loss. Under normal conditions, it is disabled to conserve

power. Additionally, enabling and setting too high a deemphasis

value on a short link can cause the receiver eye diagram to fail.

Use the deemphasis setting with caution because it can increase

electromagnetic interference (EMI). See the Memory Map section

(Register 0x413 to Register 0x422 in Memory Map) for more

details.

JTX PLL

The JTX PLL generates the serializer clock (fLR), which operates

at the JESD204B lane rate. The status of the PLL lock can be

checked in the PLL_STATUS register (Register 0x301), Bit 7

(JTX_PLL_LOCKED). This read only bit lets the user know if

the PLL has achieved lock for the specific setup.

AD9083EBZ Datasheet(PDF) 48 Page - Analog Devices

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