AD9083EBZ datasheet(46/93 Pages) AD

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AD9083

Data Sheet

Rev. 0 | Page 46 of 93

TRANSPORT

LAYER

PHYSICAL

LAYER

DATA LINK

LAYER

OUTPUT

SAMPLE

CONSTRUCTION

FRAME

CONSTRUCTION

SCRAMBLER

ALIGNMENT

CHARACTER

GENERATION

8-BIT/10-BIT

ENCODER

CROSSBAR

MUX

SERIALIZER

PROCESSED

SAMPLES

FROM ADC

SYSREF_x

SYNCINB_x

Figure 86. Data Flow

FUNCTIONAL OVERVIEW

The block diagram in Figure 86 shows the flow of data through

the JESD204B hardware from the sample input to the physical

output. The processing can be divided into layers that are

derived from the open source initiative (OSI) model, widely

used to describe the abstraction layers of communications

systems. These layers are the transport layer, data link layer,

and physical layer (serializer and output driver).

Transport Layer

The transport layer handles packing the data (consisting of

samples and optional control bits) into JESD204B frames that

are mapped to 8-bit octets. The packing of samples into frames

are determined by the JESD204B configuration parameters for

number of lanes (L), number of converters (M), the number of

octets per lane per frame (F), the number of samples per

converter per frame (S), and the number of bits in a nibble

group (sometimes called the JESD204 word size − N’).

Samples are mapped in order starting from Converter 0, then

Converter 1, and so on until Converter M − 1. If S > 1, each

sample from the converter is mapped before mapping the

samples from the next converter. Each sample is mapped into

words formed by appending converter control bits, if enabled,

to the LSBs of each sample. The words are then padded with tail

bits, if necessary, to form nibble groups (NGs) of the appropriate

size as determined by the N’ parameter. The following equation

can be used to determine the number of tail bits within a nibble

group (JESD204B word):

T = N΄ − N – CS

Data Link Layer

The data link layer is responsible for the low level functions

of passing data across the link. These include optionally

scrambling the data, inserting control characters during the

initial lane alignment sequence (ILAS) and for frame and

multiframe synchronization monitoring, and encoding 8-bit

octets into 10-bit symbols. The data link layer is also responsible

for sending the ILAS, which contains the link configuration

data used by the receiver to verify the settings in the transport

layer.

The implementation of the data link layer is discussed in the

JESD204B Link Establishment section.

Physical Layer

The physical layer consists of the high speed circuitry clocked at

the serial clock rate. In this layer, parallel data is converted into

one, two, or four lanes of high speed differential serial data. The

implementation of the Physical Layer is covered in the Physical

Layer (Driver) Outputs section.

JESD204B LINK ESTABLISHMENT

The AD9083 JESD204B transmitter (Tx) interface operates in

Subclass 0 or Subclass 1 as defined in the JEDEC Standard

JESD204B (July 2011 specification). The link establishment

process is divided into the following steps: code group synchro-

nization, initial lane alignment sequence, and user data and error

correction.

Code Group Synchronization (CGS)

CGS is the process by which the JESD204B receiver finds the

boundaries between the 10-bit symbols in the stream of data.

During the CGS phase, the JESD204B transmit block transmits

/K/ characters (/K28.5/ symbols). The receiver must locate the

/K/ characters in its input data stream using clock and data

recovery (CDR) techniques.

The receiver issues a synchronization request by asserting the

SYNCINB± pin of the AD9083 low. The JESD204B Tx then begins

sending /K/ characters. After the receiver has synchronized, it waits

for the correct reception of at least four consecutive /K/ symbols. It

then de-asserts SYNCINB±. The AD9083 then transmits an ILAS

on the following local multiframe clock (LMFC) boundary.

For more information on the code group synchronization

phase, refer to the JEDEC Standard JESD204B, July 2011,

Section 5.3.3.1.

The SYNCINB± pin operation can also be controlled by the

SPI. The SYNCINB± signal is a differential dc-coupled LVDS

mode signal by default, but it can also be driven single-ended.

The SYNCINB± pins can also be configured to run in CMOS

(single-ended) mode by setting Bit 0 in Register 0x447. When

running SYNCINB± in CMOS mode, connect the CMOS

SYNCINB signal to Pin 21 (SYNCINB+) and leave Pin 20

(SYNCINB−) disconnected.

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