LTM4680 datasheet(30/132 Pages) AD

30 / 132 page

LTM4681

Rev. 0

For more information www.analog.com

OPERATION

respond at the global addresses 0x5A and 0x5B, but use

of these addresses when attempting to recover from a

CRC issue is not recommended. All power supply rails

associated with either PWM channel of a device reporting

an invalid CRC should remain disabled until the issue is

resolved. See the Applications Information section or con-

tact the factory for details on efficient in-system EEPROM

programming, including bulk EEPROM Programming,

which the LTM4681 also supports.

The LTM4681 contains two dual internal constant fre-

quency current mode control buck regulators (channel 0

and channel 1, and channel 2 and 3) and whose power

MOSFETs are capable of fast switching speed. Reference to

the signal pins will be Name_nn, where n is either 01 or 23,

or with namen when referring to signal pins that are related

to the actual channel. The factory NVM-default switching

frequency clocks SYNC_nn at 350kHz, to which the regu-

lators synchronize their switching frequency. The default

phase-interleaving angle between the channels is 180°. A

pin-strapping resistor on FSWPH_nn_CFG configures the

frequency of the SYNC_nn clock (switching frequency) and

the channel phase relationship of the channels to each other

and with respect to the falling edge of the SYNC_nn sig-

nal. (Most possible combinations of switching frequency

and phase-angle assignments are settleable by resistor

pin programming; see Table 3. Configure the LTM4681’s

NVM to implement settings not available by resistor-pin

strapping.) When a FSWPH_nn_CFG pin-strap resistor

sets the channel phase relationship of the LTM4681’s

channels, the SYNC_nn clock is not driven by the module;

instead, SYNC_nn becomes strictly a high impedance input

and channel switching frequency is then synchronized to

SYNC_nn provided by an externally-generated clock or sib-

ling LTM4681 with pull-up resistor to VDD33_nn. Switching

frequency and phase relationship can be altered via the

I2C interface, but only when switching action is off, i.e.,

when the module is not regulating the outputs. See the

Applications Information section for details.

Programmable analog feedback loop compensation for

channel 0 to channel 3 is accomplished with a capaci-

tor connection from COMPna to SGND, and a capacitor

from COMPnb to SGND.) The COMPnb pin is for the

high frequency gain roll off and is the gm amplifier out-

put that has a programmable range, and the COMPna

pin has the programmable resistor range along with a

capacitor to SGND that sets the frequency compensa-

tion. See Programmable Loop Compensation section.

The LTM4681 module has sufficient stability margins and

good transient performance with a wide range of output

capacitors—even all-ceramic MLCCs. Table 13 provides

guidance on input and output capacitors recommended

for many common operating conditions along with

the programmable compensation settings. The Analog

Devices LTpowerCAD tool is available for transient and

stability analysis, and experienced users who prefer to

adjust the module’s feedback loop compensation param-

eters can use this tool.

POWER-UP AND INITIALIZATION

The LTM4681 is designed to provide standalone supply

sequencing and controlled turn-on and turn-off operation.

It operates from a single input supply (4.5V to 16V) while

three on-chip linear regulators generate internal 2.5V, 3.3V

and 5.5V per controller. If VINnn does not exceed 6V, and

the VBIAS pin is turned off, the INTVCC, VINnn and SVIN_nn

pins must be tied together. The controller configuration

is initialized by an internal threshold based UVLO where

VINnn must be approximately 4V and the 5.5V, 3.3V and

2.5V linear regulators must be within approximately 20%

of the regulated values. In addition to the power supply, a

PMBus RESTORE_USER_ALL or MFR_RESET command

can initialize the part too.

The VBIAS pin is the output of an internal 5.5V buck regu-

lator to improve efficiency of the circuit and minimize

power loss on the LTM4681. The VBIAS pin must exceed

approximately 4.8V, and VIN must exceed 7V before the

INTVCC LDO operates from the VBIAS pin. The VBIAS regu-

lator is powered from VIN_VBIAS and enabled with RUNP.

During initialization, the external configuration resistors

are identified and/or contents of the NVM are read into the

controller’s commands and the power train is held off. The

RUNn and FAULTn and PGOODn are held low. The LTM4681

will use the contents of Table 1 thru Table 5 to determine the

resistor defined parameters. See the Resistor Configuration

section for more details. The resistor configuration pins

only control some of the preset values of the controller.

LTM4680 Datasheet(PDF) 30 Page - Analog Devices

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