LTM4680 datasheet(23/132 Pages) AD

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LTM4681

Rev. 0

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application for digital communication to the SMBus

master(s) that nominally drive this clock. The LTM4681

will never encounter scenarios where it would need to

engage clock stretching unless SCL communication

speeds exceed 100kHz—and even then, LTM4681 will not

clock stretch unless clock stretching is enabled by means

of setting MFR_CONFIG_ALL[1] = 1b. The factory-default

NVM configuration setting has MFR_CONFIG_ALL[1] =

0b: clock stretching disabled. If communication on the

bus at clock speeds above 100kHz is required, the user’s

SMBus master(s) needs to implement clock stretching

support to assure solid serial bus communications, and

only then should MFR_CONFIG_ALL[1] be set to 1b.

When clock stretching is enabled, SCL becomes a bidi-

rectional, open-drain output pin on LTM4681.

SDA_01, SDA_23 (C10, V8): Serial Bus Data Open-Drain

Input and Output. A pull-up resistor to 3.3V is required

in the application. SDA_01 is for Channel 0 and 1, and

SDA_23 is for Channel 2 and 3.

ALERT_01, ALERT_23 (C11, W8): Open-Drain Digital

Output. A pull-up resistor to 3.3V is required in the

application only if SMBALERT interrupt detection is imple-

mented in one’s SMBus system.

SHARE_CLK_01, SHARE_CLK_23 (D8, AA11): Share

Clock, Bidirectional Open-Drain Clock Sharing Pin.

Nominally 100kHz. Used for synchronizing the time

base between multiple LTM4681s (and any other Analog

Devices products with a SHARE_CLK pin)—to realize

well-defined rail sequencing and rail tracking. Tie the

SHARE_CLK pins of all such devices together; all devices

with a SHARE_CLK pin will synchronize to the fastest

clock. A pull-up resistor to 3.3V is only required when

synchronizing the time base between devices.

TSNS0, TSNS1, TSNS2, TSNS3 (E11, E10, U8, U9):

Power stage temperature monitors for the 4channels.

See Applications Information section.

WP_01, WP_23 (E9, Y11): Write Protect Pin, Active High.

An internal 10µA current source pulls this pin to VDD33. If

WP is open circuit or logic high, only I2C writes to PAGE,

OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS and

MFR_EE_UNLOCK are supported. Additionally, Individual

faults can be cleared by writing 1b’s to bits of interest in

registers prefixed with STATUS. If WP is low, I2C writes

are unrestricted.

PIN FUNCTIONS

LTM4680 Datasheet(PDF) 23 Page - Analog Devices

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