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VR5510 Datasheet(PDF) 39 Page - NXP Semiconductors

Part # VR5510
Description  Multi-Output PMIC with SMPS and LDO
PDF  203 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

VR5510 Datasheet(HTML) 39 Page - NXP Semiconductors

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NXP Semiconductors
VR5510
Multi-Output PMIC with SMPS and LDO
12.3 Application schematic: dual-phase mode
In this configuration, BUCK1 and BUCK2 are configured in dual-phase mode to
double the output current capability. Dual-phase mode is enabled by OTP via the
VB12MULTIPH_OTP bit (CFG_ BUCK1_ 2_OTP register). The PCB layout of BUCK1
and BUCK2 must be symmetric for optimum EMC performance.
Controller
Internal
Compensation
Driver
EPAD
BUCK1_IN
VBUCK1/2
VPRE
BUCK1
BUCK1_SW
CIN_BUCK1
LBUCK1
COUT_BUCK1
BUCK1_FB
aaa-039375
Controller
Internal
Compensation
Driver
EPAD
BUCK2_IN
VPRE
BUCK2
BUCK2_SW
CIN_BUCK2
LBUCK2
COUT_BUCK2
BUCK2_FB
Figure 19. BUCK1/2 dual-phase schematic
12.4 Compensation network and stability
The internal compensation network ensures the stability and the transient response
performance of the buck converter. The error amplifier gain is configurable with the
BUCKx_COMP_OTP[2:0] bitfields (CFG_ BUCK3_ 2_OTP register) for each BUCK 1
and BUCK2 regulator. Use the default value, which should cover most use cases.
12.5 Electrical characteristics
TA = –40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless
otherwise specified. All voltages referenced to ground. Typical values based on TA =
25 °C.
Symbol
Parameter
Min
Typ
Max
Unit
BUCK1 and BUCK2
VBUCK12_IN
Input voltage range
2.5
—
5.5
V
VBUCK12
Output voltage, Configurable by OTP, 6.25 mV resolution
(<1.5 V)
0.4
—
1.8
V
Table 16. Electrical characteristics
VR5510
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 3 — 3 March 2021
39 / 203



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