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VR5510 Datasheet(PDF) 65 Page - NXP Semiconductors |
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VR5510 Datasheet(HTML) 65 Page - NXP Semiconductors |
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65 / 203 page  NXP Semiconductors VR5510 Multi-Output PMIC with SMPS and LDO TIMER_STBY_WINDOW[3:0] Configure the standby timer duration 0110 8192 ms 0111 16384 ms 1000 65536 ms 1001 131072 ms 1010 262144 ms 1011 524288 ms 1100 1048576 ms 1101 2097152 ms 1110 4194304 ms 1111 8388608 ms Table 42. Standby timer duration...continued 20.6 PWRON2 for Deep Sleep mode The PWRON2 pin manages the transition to Deep Sleep mode if both the DSM_EN_OTP bit (CFG_CLOCK_3_OTP) and the PWRON2_DSM_EN bit (M_MODE register) are set to 1. Deep Sleep mode shuts down all VR5510 regulators except the HVLDO. When the device is in Deep Sleep mode, the HVLDO regulator can only operate as an LDO at 3.3 V. Only the PWRON2 input detector is active in Deep Sleep mode, so only that pin can be used to exit the mode. VR5510 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3 — 3 March 2021 65 / 203 |
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