VR5510 datasheet(90/203 Pages) NXP

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NXP Semiconductors

VR5510

Multi-Output PMIC with SMPS and LDO

Symbol

Parameter

Min

Typ

Max

Unit

FS0B

FS0BVIL

Low level Input voltage

0.7

—

FS0BVIH

High level Input voltage

—

1.5

FS0BHYST

Input voltage hysteresis

100

—

FS0BVOL

Low level output voltage (I = 2.0 mA)

—

0.4

FS0BRPD

Internal pull down resistor

MΩ

FS0BILIM

Current limitation

4.0

—

FS0BTSC

Short to high filtering time

500

—

800

μs

FS0BFALL

FS0B Falling time

—

μs

Table 71. Electrical characteristics

22.8.4 FS0B release

When the fail-safe output FS0B is asserted low by the device due to a fault, three

conditions must be validated before allowing the pin to be released by the device. The

conditions are:

• LBIST_OK = ABIST1_OK = ABIST2_OK = 1

• Fault Error Counter = 0

• FS_RELEASE_FS0B register filled with ongoing WD_SEED bit field (FS_WD_SEED

WD_SEED[23:16]

B23

B22

B21

B20

B19

B18

B17

B16

FS_RELEASE_

FS0B

Not(B8)

Not(B9)

Not(B10)

Not(B11)

Not(B12)

Not(B13)

Not(B14)

Not(B15)

WD_SEED[15:8]

B15

B14

B13

B12

B11

B10

FS_RELEASE_

FS0B

Not(B16)

Not(B17)

Not(B18)

Not(B19)

Not(B20)

Not(B21)

Not(B22)

Not(B23)

Table 72. FS_RELEASE_FS0B register based on WD_SEED

22.8.5 STBY

STBY is an input that can be connected in the application to the MCU. The standby

input pin polarity can be programmed through the STBY_POLARITY_OTP bit

(CFG_DEVID_OTP register) to either active high in Standby mode/low in Normal mode

or active low in Standby mode/high in Normal mode.

The STBY function is enabled via the STBY_EN_OTP bit (CFG_2_OTP register).

There are two possible paths to enter Standby mode, depending on the

STBY_SAFE_DIS_OTP bit (CFG_2_OTP register) setting:

• The Standard path using only the STBY pin transition

• The Safety path using an I2C request (STBY_REQ bit in the FS_SAFE_IOS register)

and the STBY pin transition

If the Safety path is used, a standby timing window register, enabled by the

STBY_WINDOW_EN_OTP bit (CFG_ 2_OTP register), is used to define the maximum

time between the I2C request and the STBY pin transition.

VR5510

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 3 March 2021

90 / 203

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