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VR5510 Datasheet(PDF) 71 Page - NXP Semiconductors

Part # VR5510
Description  Multi-Output PMIC with SMPS and LDO
PDF  203 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

VR5510 Datasheet(HTML) 71 Page - NXP Semiconductors

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NXP Semiconductors
VR5510
Multi-Output PMIC with SMPS and LDO
The watchdog error counter value can be read by the MCU for diagnostic purposes from
the WD_ERR_CNT[3:0] bit field (FS_I_WD_CFG register).
aaa-039392
WD_ERR_LIMIT = 11
WD_ERR_LIMIT = 10
WD_ERR_LIMIT = 01
0
0
1
2
3
4
WD refresh
NOT OK
WD refresh OK
WD refresh OK
WD refresh OK
WD refresh OK
WD refresh OK
WD refresh OK
WD refresh OK
WD refresh OK
WD refresh
NOT OK
WD refresh
NOT OK
0
1
2
3
4
5
6
WD refresh
NOT OK
WD refresh
NOT OK
WD refresh
NOT OK
WD refresh
NOT OK
WD refresh
NOT OK
WD refresh
NOT OK
WD refresh OK
2
1
WD OFF
WD refresh OK
WD OFF
WD refresh OK
WD OFF
WD_ERR_LIMIT = 00
WD refresh OK
WD refresh OK
WD refresh OK
WD refresh OK
WD refresh OK
0
1
2
3
4
5
6
WD refresh OK
WD refresh
NOT OK
WD refresh
NOT OK
WD refresh
NOT OK
WD refresh OK
7
8
WD refresh
NOT OK
WD refresh
NOT OK
WD refresh
NOT OK
WD refresh
NOT OK
WD refresh OK
WD OFF
Figure 33. Watchdog error counter configurations
22.4.4 Watchdog refresh counter
The watchdog refresh strategy is available for the Challenger watchdog and the
Simple watchdog. The watchdog refresh counter is used to decrement the fault error
counter. Each time the watchdog is properly refreshed, the watchdog refresh counter
is incremented by one. Each time the watchdog refresh counter reaches its maximum
value (six by default), if the next WD refresh is also good, the fault error counter is
decremented by one. Whatever position the watchdog refresh counter is in, each time a
wrong refresh watchdog occurs, the watchdog refresh counter is reset to zero.
To allow flexibility in the application, the maximum value of the watchdog refresh counter
is configurable with the WD_RFR_LIMIT[1:0] bit field (FS_I_WD_CFG register) during the
INIT_FS phase.
WD_RFR_LIMIT[1:0]
Watchdog Refresh Counter value
00 (default)
6
01
4
10
2
11
1
Reset condition
POR
Table 47. Watchdog refresh counter configuration
The watchdog refresh counter value can be read by the MCU for diagnostic purposes
with the WD_RFR_CNT[2:0] bit field (FS_I_WD_CFG register).
VR5510
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 3 — 3 March 2021
71 / 203



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