7.5.4.2 Writes

as well as the last bit (the R/W bit) set to 0b, which signifies a write. The target acknowledges, letting the

controller know it is ready. After this, the controller starts sending the control register data to the target until the

controller has sent all the data necessary (which is sometimes only a single byte), and the controller terminates

the transmission with a STOP condition.

Writes to read-only registers or register locations outside of the register map will be ignored. The TMP114 will

not NACK under these conditions.

Figure 7-10 shows an example of writing a single word write communication.

S

A6

A5

A4

A3

A2

A1

A0

0

A

START

Target Address

0

0

0

P3

P2

P1

P0

A

0

R/W

ACK from Target

Register Pointer (N)

D14 D13 D12 D11 D10 D9

D8

A

D15

D6

D5

D4

D3

D2

D1

D0

A

D7

P

STOP

ACK from Target

ACK from Target

ACK from Target

Data to Register N MSB

Data to Register N LSB

Must be 0h

Target controls SDA line

Controller controls SDA line

Auto-Increment

Figure 7-10. Write to Single Register

Multiple writes to the same register are also possible with the TMP114. Figure 7-11 shows how the controller can

repeatedly write to the same register when the Auto-Increment bit in the control register is set to 0b.

S

A6

A5

A4

A3

A2

A1

A0

0

A

START

Target Address

0

0

0

P3

P2

P1

P0

A

0

R/W

ACK from Target

Register Pointer (N)

D14 D13 D12 D11 D10 D9

D8

A

D15

D6

D5

D4

D3

D2

D1

D0

A

D7

ACK from Target

ACK from Target

ACK from Target

Data to Register N MSB

Data to Register N LSB

Must be 0h

Target controls SDA line

Controller controls SDA line

Auto-Increment

D14 D13 D12 D11 D10 D9

D8

A

D15

D6

D5

D4

D3

D2

D1

D0

A

D7

P

STOP

ACK from Target

ACK from Target

Data to Register N MSB

Data to Register N LSB

Figure 7-11. Repeated Write to Single Register

TMP114

SNIS214 – JUNE 2021

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